Datasheet

© 2007 Microchip Technology Inc. DS39599G-page 385
PIC18F2220/2320/4220/4320
OSCTUN2 (INTRC Oscillator Tuning) ........................ 24
PIE1 (Peripheral Interrupt Enable 1) .......................... 94
PIE2 (Peripheral Interrupt Enable 2) .......................... 95
PIR1 (Peripheral Interrupt Request
(Flag) 1) ............................................................. 92
PIR2 (Peripheral Interrupt Request
(Flag) 2) ............................................................. 93
PWM1CON (PWM Configuration) ............................ 149
RCON (Reset Control) ......................................... 69, 98
RCSTA (Receive Status and Control) ...................... 197
SSPCON1 (MSSP Control 1, I
2
C Mode) ................. 166
SSPCON1 (MSSP Control 1, SPI Mode) ................. 157
SSPCON2 (MSSP Control 2,
I
2
C Master Mode) ............................................. 167
SSPSTAT (MSSP Status, I
2
C Mode) ....................... 165
SSPSTAT (MSSP Status, SPI Mode) ...................... 156
STATUS ..................................................................... 68
STKPTR (Stack Pointer) ............................................ 55
Summary .............................................................. 62–64
T0CON (Timer0 Control) .......................................... 117
T1CON (Timer1 Control) .......................................... 121
T2CON (Timer2 Control) .......................................... 127
T3CON (Timer3 Control) .......................................... 129
TRISE ...................................................................... 112
TXSTA (Transmit Status and Control) ..................... 196
WDTCON (Watchdog Timer Control) ....................... 247
Reset .......................................................................... 43, 287
Resets .............................................................................. 237
RETFIE ............................................................................ 288
RETLW ............................................................................. 288
RETURN .......................................................................... 289
Return Address Stack ........................................................ 54
Return Stack Pointer (STKPTR) ........................................ 54
Revision History ............................................................... 375
RLCF ................................................................................ 289
RLNCF ............................................................................. 290
RRCF ............................................................................... 290
RRNCF ............................................................................. 291
S
SCI. See USART
SCK .................................................................................. 155
SDI ................................................................................... 155
SDO ................................................................................. 155
Serial Clock (SCK) Pin ..................................................... 155
Serial Communication Interface. See USART.
Serial Data In (SDI) Pin .................................................... 155
Serial Data Out (SDO) Pin ............................................... 155
Serial Peripheral Interface. See SPI Mode.
SETF ................................................................................ 291
Shoot-Through Current .................................................... 149
Slave Select (SS
) Pin ....................................................... 155
SLEEP .............................................................................. 292
Sleep
OSC1 and OSC2 Pin States ...................................... 28
Software Simulator (MPLAB SIM) .................................... 302
Special Event Trigger. See Compare (CCP Module).
Special Features of the CPU ............................................ 237
Special Function Registers ................................................ 61
Map ............................................................................ 61
SPI Mode
Associated Registers ............................................... 163
Bus Mode Compatibility ........................................... 163
Effects of a Reset .................................................... 163
Master in Power-Managed Modes ........................... 163
Master Mode ............................................................ 160
Master/Slave Connection ......................................... 159
Registers ................................................................. 156
Serial Clock .............................................................. 155
Serial Data In ........................................................... 155
Serial Data Out ........................................................ 155
Slave in Power-Managed Modes ............................. 163
Slave Mode .............................................................. 161
Slave Select ............................................................. 155
SPI Clock ................................................................. 160
SS
.................................................................................... 155
SSPOV Status Flag ......................................................... 185
SSPSTAT Register
R/W
Bit .............................................................168, 169
Stack Full/Underflow Resets .............................................. 55
SUBFWB ......................................................................... 292
SUBLW ............................................................................ 293
SUBWF ............................................................................ 293
SUBWFB ......................................................................... 294
SWAPF ............................................................................ 295
T
T0CON Register
PSA Bit .................................................................... 119
T0CS Bit .................................................................. 119
T0PS2:T0PS0 Bits ................................................... 119
T0SE Bit .................................................................. 119
TABLAT Register ............................................................... 74
Table Pointer Operations (table) ........................................ 74
Table Reads/Table Writes ................................................. 59
TBLPTR Register ............................................................... 74
TBLRD ............................................................................. 296
TBLWT ............................................................................. 297
Time-out in Various Situations (table) ................................ 45
Time-out Sequence ........................................................... 44
Timer0 .............................................................................. 117
16-Bit Mode Timer Reads and Writes ...................... 119
Associated Registers ............................................... 119
Clock Source Edge Select (T0SE Bit) ..................... 119
Clock Source Select (T0CS Bit) ............................... 119
Interrupt ................................................................... 119
Operation ................................................................. 119
Prescaler. See Prescaler, Timer0.
Switching Prescaler Assignment ............................. 119
Timer1 .............................................................................. 121
16-Bit Read/Write Mode .......................................... 124
Associated Registers ............................................... 125
Interrupt ................................................................... 124
Operation ................................................................. 122
Oscillator ...........................................................121, 123
Oscillator Layout Considerations ............................. 123
Overflow Interrupt .................................................... 121
Resetting, Using a Special Event Trigger
Output (CCP) ................................................... 124
Special Event Trigger (CCP) ................................... 136
TMR1H Register ...................................................... 121
TMR1L Register
....................................................... 121
Use as a Real-Time Clock ....................................... 124