Datasheet

© 2007 Microchip Technology Inc. DS39599G-page 381
PIC18F2220/2320/4220/4320
E
ECCP ............................................................................... 141
Auto-Shutdown ........................................................ 149
And Automatic Restart ..................................... 151
Capture and Compare Modes .................................. 142
Outputs .................................................................... 142
Standard PWM Mode ............................................... 142
Start-up Considerations ........................................... 151
Effects of Power-Managed Modes on
Various Clock Sources ............................................... 28
Electrical Characteristics .................................................. 305
Enhanced Capture/Compare/PWM (ECCP) .................... 141
Capture Mode. See Capture (ECCP Module).
PWM Mode. See PWM (ECCP Module).
Enhanced CCP Auto-Shutdown ....................................... 149
Enhanced PWM Mode. See PWM (ECCP Module). ........ 143
Equations
Calculating the Minimum Required
Acquisition Time ...................................... 216
16 x 16 Signed Multiplication Algorithm ..................... 86
16 x 16 Unsigned Multiplication Algorithm ................. 86
A/D Acquisition Time ................................................ 216
A/D Minimum Holding Capacitor .............................. 216
Errata ................................................................................... 5
External Clock Input ........................................................... 21
F
Fail-Safe Clock Monitor ............................................ 237, 249
Interrupts in Power-Managed Modes ....................... 251
POR or Wake from Sleep ........................................ 251
WDT During Oscillator Failure ................................. 249
Fast Register Stack ............................................................ 56
Firmware Instructions ....................................................... 257
Flash Program Memory ...................................................... 71
Associated Registers ................................................. 79
Control Registers ....................................................... 72
Erase Sequence ........................................................ 76
Erasing ....................................................................... 76
Operation During Code-Protect ................................. 79
Reading ...................................................................... 75
TABLAT Register ....................................................... 74
Table Pointer .............................................................. 74
Boundaries Based on Operation ........................ 74
Table Pointer Boundaries .......................................... 74
Table Reads and Table Writes .................................. 71
Unexpected Termination of Write Operation .............. 79
Write Verify ................................................................ 79
Writing to .................................................................... 77
FSCM. See Fail-Safe Clock Monitor.
G
GOTO ............................................................................... 278
H
Hardware Multiplier ............................................................ 85
Introduction ................................................................ 85
Operation ................................................................... 85
Performance Comparison .......................................... 85
HSPLL ................................................................................ 20
I
I/O Ports ........................................................................... 101
I
2
C Mode
ACK
Pulse ........................................................168, 169
Acknowledge Sequence Timing .............................. 188
Baud Rate Generator .............................................. 181
Bus Collision During a Repeated
Start Condition ................................................. 192
Bus Collision During a Start Condition ..................... 190
Bus Collision During a Stop Condition ..................... 193
Clock Arbitration ...................................................... 182
Clock Stretching ....................................................... 174
Effect of a Reset ...................................................... 189
General Call Address Support ................................. 178
Master Mode ............................................................ 179
Master Mode (Reception, 7-Bit Address) ................. 187
Master Mode Operation ........................................... 180
Master Mode Reception ........................................... 185
Master Mode Repeated Start Condition Timing ....... 184
Master Mode Start Condition Timing ....................... 183
Master Mode Transmission ..................................... 185
Multi-Master Communication, Bus Collision
and Bus Arbitration .......................................... 189
Multi-Master Mode ................................................... 189
Operation ................................................................. 168
Operation in Power-Managed Mode ........................ 189
Read/Write Bit Information (R/W
Bit) ................168, 169
Registers ................................................................. 164
Serial Clock (RC3/SCK/SCL) ................................... 169
Slave Mode .............................................................. 168
Addressing ....................................................... 168
Reception ........................................................ 169
Transmission ................................................... 169
Stop Condition Timing ............................................. 188
ID Locations ..............................................................237, 255
INCF ................................................................................ 278
INCFSZ ............................................................................ 279
In-Circuit Debugger .......................................................... 255
In-Circuit Serial Programming (ICSP) .......................237, 255
Indirect Addressing
INDF and FSR Registers ........................................... 66
Operation ................................................................... 66
Indirect Addressing Operation ........................................... 67
Indirect File Operand ......................................................... 59
INFSNZ ............................................................................ 279
Initialization Conditions for all Registers .......................46–49
Instruction Cycle ................................................................ 57
Instruction Flow/Pipelining ................................................. 57
Instruction Format ............................................................ 259
Instruction Set .................................................................. 257
ADDLW .................................................................... 263
ADDWF .................................................................... 263
ADDWFC ................................................................. 264
ANDLW .................................................................... 264
ANDWF .................................................................... 265
BC ............................................................................ 265
BCF ......................................................................... 266
BN
............................................................................ 266
BNC ......................................................................... 267
BNN ......................................................................... 267
BNOV ...................................................................... 268
BNZ ......................................................................... 268
BOV ......................................................................... 271
BRA ......................................................................... 269
BSF .......................................................................... 269