Datasheet

PIC18F2220/2320/4220/4320
DS39599G-page 346 © 2007 Microchip Technology Inc.
FIGURE 26-23: A/D CONVERSION TIMING
TABLE 26-25: A/D CONVERSION REQUIREMENTS
Param
No.
Symbol Characteristic Min Max Units Conditions
130 T
AD A/D Clock Period PIC18FXX20 1.6 20
(2)
μsTOSC based, VREF ≥ 3.0V
PIC18LFXX20 3.0 20
(2)
μsTOSC based, VREF full range
PIC18FXX20 2.0 6.0 μs A/D RC mode
PIC18LFXX20 3.0 9.0 μs A/D RC mode
131 T
CNV Conversion Time
(not including acquisition time)
(1)
11 12 TAD
Note 1: ADRES register may be read on the following TCY cycle.
2: The time of the A/D clock period is dependent on the device frequency and the T
AD clock divider.
131
130
132
BSF ADCON0, GO
Q4
A/D CLK
A/D DATA
ADRES
ADIF
GO
SAMPLE
OLD_DATA
SAMPLING STOPPED
DONE
NEW_DATA
(Note 2)
987 21 0
Note 1: If the A/D clock source is selected as RC, a time of T
CY is added before the A/D clock starts. This allows the SLEEP instruction to be
executed.
2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
. . .
. . .
TCY