Datasheet

PIC18F2220/2320/4220/4320
DS39599G-page 344 © 2007 Microchip Technology Inc.
FIGURE 26-21: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
TABLE 26-22: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
FIGURE 26-22: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
TABLE 26-23: USART SYNCHRONOUS RECEIVE REQUIREMENTS
121
121
120
122
RC6/TX/CK
RC7/RX/DT
pin
pin
Note: Refer to Figure 26-5 for load conditions.
Param
No.
Symbol Characteristic Min Max Units Conditions
120 T
CKH2DTV SYNC XMIT (MASTER & SLAVE)
Clock High to Data Out Valid PIC18FXX20 — 40 ns
PIC18LFXX20 — 100 ns
121 T
CKRF Clock Out Rise Time and Fall Time
(Master mode)
PIC18FXX20 — 20 ns
PIC18LFXX20 — 50 ns
122 TDTRF Data Out Rise Time and Fall Time PIC18FXX20 — 20 ns
PIC18LFXX20 — 50 ns
125
126
RC6/TX/CK
RC7/RX/DT
pin
pin
Note: Refer to Figure 26-5 for load conditions.
Param.
No.
Symbol Characteristic Min Max Units Conditions
125 T
DTV2CKL SYNC RCV (MASTER & SLAVE)
Data Hold before CK ↓ (DT hold time) 10 — ns
126 T
CKL2DTL Data Hold after CK ↓ (DT hold time) 15 — ns