Datasheet

PIC18F2220/2320/4220/4320
DS39599G-page 342 © 2007 Microchip Technology Inc.
FIGURE 26-19: MASTER SSP I
2
C™ BUS START/STOP BITS TIMING WAVEFORMS
TABLE 26-20: MASTER SSP I
2
C™ BUS START/STOP BITS REQUIREMENTS
FIGURE 26-20: MASTER SSP I
2
C™ BUS DATA TIMING
Note: Refer to Figure 26-5 for load conditions.
91
93
SCL
SDA
Start
Condition
Stop
Condition
90
92
Param.
No.
Symbol Characteristic Min Max Units Conditions
90 T
SU:STA Start condition 100 kHz mode 2(TOSC)(BRG + 1) — ns Only relevant for
Repeated Start condition
Setup time 400 kHz mode 2(TOSC)(BRG + 1) —
1 MHz mode
(1)
2(TOSC)(BRG + 1) —
91 THD:STA Start condition 100 kHz mode 2(TOSC)(BRG + 1) — ns After this period, the first
clock pulse is generated
Hold time 400 kHz mode 2(TOSC)(BRG + 1) —
1 MHz mode
(1)
2(TOSC)(BRG + 1) —
92 TSU:STO Stop condition 100 kHz mode 2(TOSC)(BRG + 1) — ns
Setup time 400 kHz mode 2(TOSC)(BRG + 1) —
1 MHz mode
(1)
2(TOSC)(BRG + 1) —
93 THD:STO Stop condition 100 kHz mode 2(TOSC)(BRG + 1) — ns
Hold time 400 kHz mode 2(TOSC)(BRG + 1) —
1 MHz mode
(1)
2(TOSC)(BRG + 1) —
Note 1: Maximum pin capacitance = 10 pF for all I
2
C pins.
Note: Refer to Figure 26-5 for load conditions.
90
91 92
100
101
103
106
107
109
109
110
102
SCL
SDA
In
SDA
Out