Datasheet

© 2007 Microchip Technology Inc. DS39599G-page 339
PIC18F2220/2320/4220/4320
TABLE 26-17: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)
FIGURE 26-17: I
2
C™ BUS START/STOP BITS TIMING
Param
No.
Symbol Characteristic Min Max Units Conditions
70 T
SSL2SCH,
T
SSL2SCL
SS
↓ to SCK ↓ or SCK ↑ Input TCY —ns
71 T
SCH SCK Input High Time
(Slave mode)
Continuous 1.25 TCY + 30 — ns
71A Single Byte 40 — ns (Note 1)
72 T
SCL SCK Input Low Time
(Slave mode)
Continuous 1.25 TCY + 30 — ns
72A Single Byte 40 — ns (Note 1)
73A T
B2B Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 — ns (Note 2)
74 TSCH2DIL,
T
SCL2DIL
Hold Time of SDI Data Input to SCK Edge 100 — ns
75 T
DOR SDO Data Output Rise Time PIC18FXX20 — 25 ns
PIC18LFXX20 45 ns
76 TDOF SDO Data Output Fall Time — 25 ns
77 T
SSH2DOZSS↑ to SDO Output High-Impedance 10 50 ns
78 T
SCR SCK Output Rise Time
(Master mode)
PIC18FXX20 — 25 ns
PIC18LFXX20 — 45 ns
79 TSCF SCK Output Fall Time (Master mode) — 25 ns
80 T
SCH2DOV,
T
SCL2DOV
SDO Data Output Valid after SCK
Edge
PIC18FXX20 — 50 ns
PIC18LFXX20 — 100 ns
82 TSSL2DOV SDO Data Output Valid after SS ↓
Edge
PIC18FXX20 — 50 ns
PIC18LFXX20 — 100 ns
83 TscH2ssH,
TscL2ssH
SS
↑ after SCK edge 1.5 TCY + 40 — ns
Note 1: Requires the use of Parameter # 73A.
2: Only if Parameter # 71A and # 72A are used.
Note: Refer to Figure 26-5 for load conditions.
91
92
93
SCL
SDA
Start
Condition
Stop
Condition
90