Datasheet

© 2007 Microchip Technology Inc. DS39599G-page 335
PIC18F2220/2320/4220/4320
TABLE 26-13: PARALLEL SLAVE PORT REQUIREMENTS (PIC18F4X20)
FIGURE 26-13: EXAMPLE SPI MASTER MODE TIMING (CKE = 0)
Param.
No.
Symbol Characteristic Min Max Units Conditions
62 T
DTV2WRH Data In Valid Before WR ↑ or CS ↑
(setup time)
20 — ns
63 T
WRH2DTIWR ↑ or CS ↑ to Data–In
Invalid (hold time)
PIC18FXX20 20 — ns
PIC18LFXX20 35 — ns
64 T
RDL2DTVRD ↓ and CS ↓ to Data–Out Valid — 80 ns
65 T
RDH2DTIRD ↑ or CS ↓ to Data–Out Invalid 10 30 ns
66 T
IBFINH Inhibit of the IBF Flag bit being Cleared from
WR
↑ or CS ↑
—3 T
CY
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
70
71 72
73
74
75, 76
78
79
80
79
78
MSb LSb
bit 6 - - - - - -1
MSb In
LSb In
bit 6 - - - -1
Note: Refer to Figure 26-5 for load conditions.