Datasheet

PIC18F2220/2320/4220/4320
DS39599G-page 332 © 2007 Microchip Technology Inc.
TABLE 26-10: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET REQUIREMENTS
FIGURE 26-10: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
Param.
No.
Symbol Characteristic Min Typ Max Units Conditions
30 T
MCLMCLR Pulse Width (low) 2 — — μs
31 T
WDT Watchdog Timer Time-out Period (no postscaler) 3.48 4.00 4.71 ms
32 T
OST Oscillation Start-up Timer Period 1024 TOSC — 1024 TOSC —TOSC = OSC1 period
33 T
PWRT Power-up Timer Period 57.0 65.5 77.2 ms
34 TIOZ I/O High-Impedance from MCLR
Low or
Watchdog Timer Reset
—2—μs
35 T
BOR Brown-out Reset Pulse Width 200 — — μsVDD ≤ BVDD (see
D005A)
36 T
IVRST Time for Internal Reference Voltage to become
stable
—2050μs
37 T
LVD Low-Voltage Detect Pulse Width 200 — — μsVDD ≤ VLVD
Note: Refer to Figure 26-5 for load conditions.
46
47
45
48
41
42
40
T0CKI
T1OSO/T1CKI
TMR0 or
TMR1