Datasheet

PIC18F2220/2320/4220/4320
DS39599G-page 330 © 2007 Microchip Technology Inc.
FIGURE 26-7: CLKO AND I/O TIMING
TABLE 26-9: CLKO AND I/O TIMING REQUIREMENTS
Note: Refer to Figure 26-5 for load conditions.
OSC1
CLKO
I/O pin
(Input)
I/O pin
(Output)
Q4
Q1
Q2 Q3
10
13
14
17
20, 21
19
18
15
11
12
16
Old Value
New Value
Param
No.
Symbol Characteristic Min Typ Max Units Conditions
10 T
OSH2CKLOSC1 ↑ to CLKO ↓ — 75 200 ns (1)
11 TOSH2CKHOSC1 ↑ to CLKO ↑ — 75 200 ns (1)
12 TCKR CLKO Rise Time — 35 100 ns (1)
13 T
CKF CLKO Fall Time — 35 100 ns (1)
14 TCKL2IOVCLKO ↓ to Port Out Valid — — 0.5 TCY + 20 ns (1)
15 TIOV2CKH Port In Valid before CLKO ↑ 0.25 TCY + 25 — — ns (1)
16 T
CKH2IOI Port In Hold after CLKO ↑ 0——ns(1)
17 TOSH2IOVOSC1↑ (Q1 cycle) to Port Out Valid — 50 150 ns
18 T
OSH2IOIOSC1↑ (Q2 cycle) to Port
Input Invalid
(I/O in hold time)
PIC18FXX20 100 — — ns
18A PIC18LFXX20 200 — — ns
19 TIOV2OSH Port Input Valid to OSC1↑ (I/O in setup time) 0 — — ns
20 T
IOR Port Output Rise Time PIC18FXX20 — 10 25 ns
20A PIC18LFXX20 — — 60 ns
21 TIOF Port Output Fall Time PIC18FXX20 — 10 25 ns
21A PIC18LFXX20 — — 60 ns
Note 1: Measurements are taken in RC mode, where CLKO output is 4 x T
OSC.