Datasheet

PIC18F2220/2320/4220/4320

2.6.2 OSCTUNE REGISTER

The internal oscillator block is calibrated at the factory

to produce an INTOSC output frequency of approxi-

mately 8 MHz. (See parameters F14–F19 in

Table 26-8.)

The INTOSC frequency can be adjusted using the

TUN5:TUN1 bits in the OSCTUNE register

OSCTUNE<5:1>. OSCTUNE<0> has no effect, but is

readable and writable, enabling changes of the

INTOSC frequency using two increment or decrement

instructions.

The internal oscillator’s output can be adjusted in the

user’s application. This is done by writing to the

OSCTUNE register (Register 2-1). The tuning

sensitivity is constant throughout the tuning range.

When the OSCTUNE register is modified, the INTOSC

and INTRC frequencies begin shifting to the new fre-

quency. The INTOSC and INTRC clocks will stabilize at

the new frequency within 100 μs. Code execution

continues during this shift.

There is no indication when the shift occurs. Operation

of features that depend on the INTRC clock source

frequency also will be affected by the change in

frequency. This includes the WDT, Fail-Safe Clock

Monitor and peripherals.

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — TUN5 TUN4 TUN3 TUN2 TUN1 TUN0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’

bit 5-1 TUN<5:1>: Frequency Tuning bits – Adjusts the frequency of INTOSC. Can adjust INTRC, depending

on TUNSEL (OSCTUN2<7>)

011111 = Maximum frequency

• •

000001

000000 = Center frequency. Oscillator module is running at the calibrated frequency.

111111

• •

100000 = Minimum frequency

bit 0 TUN<0>: A placeholder with no effect on the INTRC frequency. Provided to facilitate incrementation

and decrementation of the OSCTUN2 register and adjustment of the INTRC frequency.