Datasheet

© 2007 Microchip Technology Inc. DS39599G-page 247
PIC18F2220/2320/4220/4320
TABLE 23-2: SUMMARY OF WATCHDOG TIMER REGISTERS
REGISTER 23-14: WDTCON: WATCHDOG TIMER CONTROL REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
— — — — — — —SWDTEN
(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-1 Unimplemented: Read as ‘0’
bit 0 SWDTEN: Software Controlled Watchdog Timer Enable bit
(1)
1 = Watchdog Timer is on
0 = Watchdog Timer is off
Note 1: This bit has no effect if the Configuration bit, WDTEN (CONFIG2H<0>), is enabled.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
CONFIG2H
— — — WDTPS3 WDTPS2 WDTPS2 WDTPS0 WDTEN
RCON
IPEN — — RI TO PD POR BOR
WDTCON — — — — — — —SWDTEN
Legend: Shaded cells are not used by the Watchdog Timer.