Datasheet

PIC18F2220/2320/4220/4320
DS39599G-page 228 © 2007 Microchip Technology Inc.
FIGURE 21-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
21.2 Voltage Reference Accuracy/Error
The full range of voltage reference cannot be realized
due to the construction of the module. The transistors
on the top and bottom of the resistor ladder network
(Figure 21-1) keep CV
REF from approaching the refer-
ence source rails. The voltage reference is derived
from V
DD; therefore, the CVREF output changes with
fluctuations in V
DD. The tested absolute accuracy of
the voltage reference can be found in Section 26.0
“Electrical Characteristics”.
21.3 Operation in Power-Managed
Modes
The contents of the CVRCON register are not affected
by entry to or exit from power-managed modes. To min-
imize current consumption in power-managed modes,
the voltage reference module should be disabled; how-
ever, this can cause an interrupt from the comparators
so the comparator interrupt should also be disabled
while the CVRCON register is being modified.
21.4 Effects of a Reset
A device Reset disables the voltage reference by clear-
ing the CVRCON register. This also disconnects the
reference from the RA2 pin, selects the high-voltage
range and selects the lowest voltage tap from the
resistor divider.
21.5 Connection Considerations
The voltage reference module operates independently
of the comparator module. The output of the reference
generator may be output using the RA2 pin if the
CVROE bit is set. Enabling the voltage reference out-
put onto the RA2 pin, with an input signal present, will
increase current consumption.
The RA2 pin can be used as a simple D/A output with
limited drive capability. Due to the limited current drive
capability, an external buffer must be used on the
voltage reference output for external connections to
V
REF. Figure 21-2 shows an example buffering
technique.
8R
CVR3
CVR0
(From CVRCON<3:0>)
16-1 Analog Mux
8R
R
R
R
R
CVREN
CV
REF
16 Stages
VDD
CVRR
CVROE
RA2/AN2/V
REF-/CVREF