Datasheet

PIC18F2220/2320/4220/4320
DS39599G-page 220 © 2007 Microchip Technology Inc.
19.8 Use of the CCP2 Trigger
An A/D conversion can be started by the “Special Event
Trigger” of the CCP2 module. This requires that the
CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be pro-
grammed as ‘1011’ and that the A/D module is enabled
(ADON bit is set). When the trigger occurs, the GO/
DONE
bit will be set, starting the A/D acquisition and
conversion and the Timer1 (or Timer3) counter will be
reset to zero. Timer1 (or Timer3) is reset to automati-
cally repeat the A/D acquisition period with minimal
software overhead (moving ADRESH/ADRESL to the
desired location). The appropriate analog input chan-
nel must be selected and the minimum acquisition
period is either timed by the user or an appropriate
TACQ time, selected before the “Special Event Trigger”,
sets the GO/DONE
bit (starts a conversion).
If the A/D module is not enabled (ADON is cleared), the
“Special Event Trigger” will be ignored by the A/D
module but will still reset the Timer1 (or Timer3)
counter.
TABLE 19-2: SUMMARY OF A/D REGISTERS
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Value on
all other
Resets
INTCON GIE/
GIEH
PEIE/
GIEL
TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 0000 0000 0000
PIR1
PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1
PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
IPR1
PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111
PIR2
OSCFIF CMIF — EEIF BCLIF LVDIF TMR3IF CCP2IF 00-0 0000 00-0 0000
PIE2
OSCFIE CMIE — EEIE BCLIE LVDIE TMR3IE CCP2IE 00-0 0000 00-0 0000
IPR2
OSCFIP CMIP — EEIP BCLIP LVDIP TMR3IP CCP2IP 11-1 1111 11-1 1111
ADRESH A/D Result Register High Byte xxxx xxxx uuuu uuuu
ADRESL A/D Result Register Low Byte xxxx xxxx uuuu uuuu
ADCON0
— — CHS3 CHS3 CHS1 CHS0 GO/DONE ADON --00 0000 --00 0000
ADCON1
— — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0qqq --00 0qqq
ADCON2 ADFM
— ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0-00 0000 0-00 0000
PORTA RA7
(4)
RA6
(4)
RA5 RA4 RA3 RA2 RA1 RA0 --0x 0000 --0u 0000
TRISA TRISA7
(4)
TRISA6
(4)
--11 1111 --11 1111
PORTB Read PORTB pins, Write LATB Latch xxxx xxxx uuuu uuuu
TRISB PORTB Data Direction Register 1111 1111 1111 1111
LATB PORTB Output Data Latch xxxx xxxx uuuu uuuu
PORTE
(2)
— — — —RE3
(1)
Read PORTE pins, Write LATE
(4)
---- xxxx ---- uuuu
TRISE
(2)
IBF OBE IBOV PSPMODE — PORTE Data Direction 0000 -111 0000 -111
LATE
(2)
— — — — PORTE Output Data Latch ---- -xxx ---- -uuu
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’, q = value depends on condition.
Shaded cells are not used for A/D conversion.
Note 1: The RE3 port bit is available as an input-only pin only in 40-pin devices and when Master Clear functionality is disabled
(CONFIG3H<7>=
0).
2: This register is not implemented on PIC18F2X20 devices and reads back 0x00.
3: These pins may be configured as port pins depending on the oscillator mode selected.