Datasheet

© 2007 Microchip Technology Inc. DS39599G-page 17
PIC18F2220/2320/4220/4320
PORTD is a bidirectional I/O port or a Parallel Slave Port
(PSP) for interfacing to a microprocessor port. These pins
have TTL input buffers when PSP module is enabled.
RD0/PSP0
RD0
PSP0
19 38 38
I/O
I/O
ST
TTL
Digital I/O.
Parallel Slave Port data.
RD1/PSP1
RD1
PSP1
20 39 39
I/O
I/O
ST
TTL
Digital I/O.
Parallel Slave Port data.
RD2/PSP2
RD2
PSP2
21 40 40
I/O
I/O
ST
TTL
Digital I/O.
Parallel Slave Port data.
RD3/PSP3
RD3
PSP3
22 41 41
I/O
I/O
ST
TTL
Digital I/O.
Parallel Slave Port data.
RD4/PSP4
RD4
PSP4
27 2 2
I/O
I/O
ST
TTL
Digital I/O.
Parallel Slave Port data.
RD5/PSP5/P1B
RD5
PSP5
P1B
28 3 3
I/O
I/O
O
ST
TTL
—
Digital I/O.
Parallel Slave Port data.
Enhanced CCP1 output.
RD6/PSP6/P1C
RD6
PSP6
P1C
29 4 4
I/O
I/O
O
ST
TTL
—
Digital I/O.
Parallel Slave Port data.
Enhanced CCP1 output.
RD7/PSP7/P1D
RD7
PSP7
P1D
30 5 5
I/O
I/O
O
ST
TTL
—
Digital I/O.
Parallel Slave Port data.
Enhanced CCP1 output.
TABLE 1-3: PIC18F4220/4320 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
Pin
Type
Buffer
Type
Description
PDIP TQFP QFN
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
OD = Open-drain (no diode to V
DD)
Note 1: Alternate assignment for CCP2 when CCP2MX is cleared.
2: Default assignment for CCP2 when CCP2MX (CONFIG3H<0>) is set.