Datasheet

© 2007 Microchip Technology Inc. DS39599G-page 181
PIC18F2220/2320/4220/4320
17.4.7 BAUD RATE
In I
2
C Master mode, the Baud Rate Generator (BRG)
reload value is placed in the lower 7 bits of the
SSPADD register (Register 17-17). When a write
occurs to SSPBUF, the Baud Rate Generator will auto-
matically begin counting. The BRG counts down to ‘0’
and stops until another reload has taken place. The
BRG count is decremented twice per instruction cycle
(T
CY) on the Q2 and Q4 clocks. In I
2
C Master mode, the
BRG is reloaded automatically.
Once the given operation is complete (i.e., transmis-
sion of the last data bit is followed by ACK
), the internal
clock will automatically stop counting and the SCL pin
will remain in its last state.
Table 17-3 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPADD.
17.4.7.1 Baud Rate Generation in
Power-Managed Modes
When the device is operating in a power-managed
mode, the clock source to the Baud Rate Generator
may change frequency or stop, depending on the
power-managed mode and clock source selected.
In most power modes, the Baud Rate Generator
continues to be clocked but may be clocked from the
primary clock (selected in a Configuration Word), the
secondary clock (Timer1 oscillator at 32.768 kHz) or
the internal oscillator block (one of eight frequencies
between 31 kHz and 8 MHz). If the Sleep mode is
selected, all clocks are stopped and the Baud Rate
Generator will not be clocked.
FIGURE 17-17: BAUD RATE GENERATOR BLOCK DIAGRAM
TABLE 17-3: I
2
C CLOCK RATE W/BRG
SSPM3:SSPM0
BRG Down Counter
CLKO
F
OSC/4
SSPADD<6:0>
SSPM3:SSPM0
SCL
Reload
Control
Reload
FOSC FCY FCY * 2
SSPADD VALUE
(See Register 17-4,
Mode 1000)
F
SCL
(2)
(2 Rollovers of BRG)
40 MHz 10 MHz 20 MHz 18h 400 kHz
(1)
40 MHz 10 MHz 20 MHz 1Fh 312.5 kHz
40 MHz 10 MHz 20 MHz 63h 100 kHz
16 MHz 4 MHz 8 MHz 09h 400 kHz
(1)
16 MHz 4 MHz 8 MHz 0Bh 308 kHz
16 MHz 4 MHz 8 MHz 27h 100 kHz
4 MHz 1 MHz 2 MHz 02h 333 kHz
(1)
4 MHz 1 MHz 2 MHz 09h 100kHz
4 MHz 1 MHz 2 MHz 00h 1 MHz
(1)
Note 1: The I
2
C interface does not conform to the 400 kHz I
2
C specification (which applies to rates greater than
100 kHz) in all details, but may be used with care where higher rates are required by the application.
2: Actual clock rate will depend on bus conditions. Bus capacitance can increase rise time and extend the low
time of the clock period, reducing the effective clock frequency (see Section 17.4.7.2 “Clock Arbitration”).