Datasheet

PIC18F2220/2320/4220/4320

17.4.4.5 Clock Synchronization and

the CKP bit (SEN = 1)

The SEN bit is also used to synchronize writes to the

CKP bit. If a user clears the CKP bit, the SCL output is

forced to ‘0’. When the SEN bit is set to ‘1’, setting the

CKP bit will not assert the SCL output low until the

SCL output is already sampled low. If the user

attempts to drive SCL low, the CKP bit will not assert

the SCL line until an external I

C master device has

already asserted the SCL line. The SCL output will

remain low until the CKP bit is set and all other

devices on the I

C bus have deasserted SCL. This

ensures that a write to the CKP bit will not violate the

minimum high time requirement for SCL (see

Figure 17-12).

FIGURE 17-12: CLOCK SYNCHRONIZATION TIMING

Note: If the SEN bit is ‘0’, clearing the CKP bit

will result in immediately driving the SCL

output to ‘0’ regardless of the current

state.

SDA

SCL

DX-1DX

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

SSPCON1

CKP

Master device

deasserts clock

Master device

asserts clock