Datasheet

PIC18F2220/2320/4220/4320
DS39599G-page 110 © 2007 Microchip Technology Inc.
FIGURE 10-12: BLOCK DIAGRAM OF RD4:RD0 PINS
TABLE 10-7: PORTD FUNCTIONS
TABLE 10-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Name Bit# Buffer Type Function
RD0/PSP0 bit 0 ST/TTL
(1)
Input/output port pin or Parallel Slave Port bit 0.
RD1/PSP1 bit 1 ST/TTL
(1)
Input/output port pin or Parallel Slave Port bit 1.
RD2/PSP2 bit 2 ST/TTL
(1)
Input/output port pin or Parallel Slave Port bit 2.
RD3/PSP3 bit 3 ST/TTL
(1)
Input/output port pin or Parallel Slave Port bit 3.
RD4/PSP4 bit 4 ST/TTL
(1)
Input/output port pin or Parallel Slave Port bit 4.
RD5/PSP5/P1B bit 5 ST/TTL
(1)
Input/output port pin, Parallel Slave Port bit 5 or Enhanced PWM output P1B.
RD6/PSP6/P1C bit 6 ST/TTL
(1)
Input/output port pin, Parallel Slave Port bit 6 or Enhanced PWM output P1C.
RD7/PSP7/P1D bit 7 ST/TTL
(1)
Input/output port pin, Parallel Slave Port bit 7 or Enhanced PWM output P1D.
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Value on
all other
Resets
PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx uuuu uuuu
LATD LATD Data Latch Register xxxx xxxx uuuu uuuu
TRISD PORTD Data Direction Register 1111 1111 1111 1111
TRISE
IBF OBF IBOV PSPMODE — PORTE Data Direction bits 0000 -111 0000 -111
CCP1CON P1M1 P1M0
DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by PORTD.
Data Bus
WR LATD
WR TRISD
Data Latch
TRIS Latch
RD TRISD
I/O pin
(1)
QD
CK
QD
CK
EN
QD
EN
RD LATD
or
PORTD
0
1
Q
Q
0
1
P
N
V
DD
VSS
0
1
RD PORTD
PSP Write
PSP Read
Note 1: I/O pins have diode protection to VDD and VSS.
TTL Buffer
Schmitt Trigger
Input Buffer
PORTD/CCP1 Select
PSPMODE