PIC18F2220/2320/4220/4320 Data Sheet 28/40/44-Pin High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology © 2007 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PIC18F2220/2320/4220/4320 28/40/44-Pin High-Performance, Enhanced Flash MCUs with 10-Bit A/D and nanoWatt Technology Low-Power Features: Peripheral Highlights: • Power-Managed modes: - Run: CPU on, peripherals on - Idle: CPU off, peripherals on - Sleep: CPU off, peripherals off • Power Consumption modes: - PRI_RUN: 150 μA, 1 MHz, 2V - PRI_IDLE: 37 μA, 1 MHz, 2V - SEC_RUN: 14 μA, 32 kHz, 2V - SEC_IDLE: 5.8 μA, 32 kHz, 2V - RC_RUN: 110 μA, 1 MHz, 2V - RC_IDLE: 52 μA, 1 MHz, 2V - Sleep: 0.
PIC18F2220/2320/4220/4320 Pin Diagrams 28-Pin SPDIP, SOIC 40-Pin PDIP MCLR/VPP/RE3 RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ RA4/T0CKI/C1OUT RA5/AN4/SS/LVDIN/C2OUT RE0/AN5/RD RE1/AN6/WR RE2/AN7/CS VDD VSS OSC1/CLKI/RA7 OSC2/CLKO/RA6 RC0/T1OSO/T1CKI RC1/T1OSI/CCP2* RC2/CCP1/P1A RC3/SCK/SCL RD0/PSP0 RD1/PSP1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 28 27 26 25 24 23 22 21 20 19 18 17 16 15 PIC18F2220 PIC18F2320 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PIC18F4220 PIC18F4320 MCLR/VPP RA0/AN0
PIC18F2220/2320/4220/4320 RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 RD1/PSP1 RD0/PSP0 RC3/SCK/SCL RC2/CCP1/P1A RC1/T1OSI/CCP2* NC Pin Diagrams (Cont.
PIC18F2220/2320/4220/4320 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 7 2.0 Oscillator Configurations ............................................................................................................................................................ 19 3.0 Power-Managed Modes .............................................................
PIC18F2220/2320/4220/4320 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.
PIC18F2220/2320/4220/4320 NOTES: DS39599G-page 6 © 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320 1.0 DEVICE OVERVIEW This document contains device-specific information for the following devices: • PIC18F2220 • PIC18F4220 • PIC18F2320 • PIC18F4320 This family offers the advantages of all PIC18 microcontrollers – namely, high computational performance at an economical price with the addition of highendurance Enhanced Flash program memory.
PIC18F2220/2320/4220/4320 1.3 Details on Individual Family Members 3. Devices in the PIC18F2220/2320/4220/4320 family are available in 28-pin (PIC18F2X20) and 40/44-pin (PIC18F4X20) packages. Block diagrams for the two groups are shown in Figure 1-1 and Figure 1-2. 4. The devices are differentiated from each other in five ways: 5. 1. All other features for devices in this family are identical. These are summarized in Table 1-1. 2.
PIC18F2220/2320/4220/4320 FIGURE 1-1: PIC18F2220/2320 BLOCK DIAGRAM Data Bus<8> 21 Table Pointer <2> 21 8 8 8 PORTA Data Latch 8 RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ RA4/T0CKI/C1OUT RA5/AN4/SS/LVDIN/C2OUT OSC2/CLKO/RA6(2) OSC1/CLKI/RA7(2) Data RAM (512 Bytes) inc/dec logic 21 Address Latch 20 Address Latch Program Memory (4 Kbytes) PCLATU PCLATH 12 Address<12> PCU PCH PCL Program Counter Data Latch 4 BSR 31 Level Stack 16 Decode Table Latch 8 12 4 FSR0 Bank0, F FSR1 FSR
PIC18F2220/2320/4220/4320 FIGURE 1-2: PIC18F4220/4320 BLOCK DIAGRAM Data Bus<8> PORTA 21 Table Pointer <2> 21 8 8 Data Latch 8 8 RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ RA4/T0CKI/C1OUT RA5/AN4/SS/LVDIN/C2OUT OSC2/CLKO/RA6(3) OSC1/CLKI/RA7(3) Data RAM (512 Bytes) inc/dec logic 21 Address Latch 20 Address Latch Program Memory (8 Kbytes) PCLATU PCLATH 12(2) Address<12> PCU PCH PCL Program Counter Data Latch 4 BSR 31 Level Stack 16 Decode Table Latch 8 12 4 FSR0 Bank0, F FSR1 F
PIC18F2220/2320/4220/4320 TABLE 1-2: PIC18F2220/2320 PINOUT I/O DESCRIPTIONS Pin Name Pin Number Pin Buffer PDIP SOIC Type Type 1 MCLR/VPP MCLR 1 I VPP P 9 OSC1/CLKI/RA7 OSC1 9 I CLKI I RA7 I/O OSC2/CLKO/RA6 OSC2 ST 10 Description Master Clear (input) or programming voltage (input). Master Clear (Reset) input. This pin is an active-low Reset to the device. Programming voltage input. Oscillator crystal or external clock input. Oscillator crystal input or external clock source input.
PIC18F2220/2320/4220/4320 TABLE 1-2: PIC18F2220/2320 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number Pin Buffer PDIP SOIC Type Type Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.
PIC18F2220/2320/4220/4320 TABLE 1-2: PIC18F2220/2320 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number Pin Buffer PDIP SOIC Type Type Description PORTC is a bidirectional I/O port. RC0/T1OSO/T1CKI RC0 T1OSO T1CKI 11 RC1/T1OSI/CCP2 RC1 T1OSI CCP2(2) 12 RC2/CCP1/P1A RC2 CCP1 P1A 13 RC3/SCK/SCL RC3 SCK SCL 14 RC4/SDI/SDA RC4 SDI SDA 15 RC5/SDO RC5 SDO 16 RC6/TX/CK RC6 TX CK 17 RC7/RX/DT RC7 RX DT 18 VSS VDD 11 ST — ST Digital I/O. Timer1 oscillator output.
PIC18F2220/2320/4220/4320 TABLE 1-3: PIC18F4220/4320 PINOUT I/O DESCRIPTIONS Pin Name MCLR/VPP/RE3 MCLR Pin Number Pin Buffer Type Type PDIP TQFP QFN 1 18 18 VPP RE3 OSC1/CLKI/RA7 OSC1 13 30 ST P I ST 32 I CLKI I RA7 OSC2/CLKO/RA6 OSC2 I I/O 14 31 Description Master Clear (input) or programming voltage (input). Master Clear (Reset) input. This pin is an active-low Reset to the device. Programming voltage input. Digital input. Oscillator crystal or external clock input.
PIC18F2220/2320/4220/4320 TABLE 1-3: Pin Name PIC18F4220/4320 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Type Type PDIP TQFP QFN Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.
PIC18F2220/2320/4220/4320 TABLE 1-3: PIC18F4220/4320 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number Pin Buffer Type Type PDIP TQFP QFN Description PORTC is a bidirectional I/O port. RC0/T1OSO/T1CKI RC0 T1OSO T1CKI 15 RC1/T1OSI/CCP2 RC1 T1OSI CCP2(2) 16 RC2/CCP1/P1A RC2 CCP1 P1A 17 RC3/SCK/SCL RC3 SCK SCL 18 RC4/SDI/SDA RC4 SDI SDA 23 RC5/SDO RC5 SDO 24 RC6/TX/CK RC6 TX CK 25 RC7/RX/DT RC7 RX DT 26 32 35 36 37 42 43 44 1 34 I/O O I ST — ST Digital I/O.
PIC18F2220/2320/4220/4320 TABLE 1-3: Pin Name PIC18F4220/4320 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Type Type PDIP TQFP QFN Description PORTD is a bidirectional I/O port or a Parallel Slave Port (PSP) for interfacing to a microprocessor port. These pins have TTL input buffers when PSP module is enabled.
PIC18F2220/2320/4220/4320 TABLE 1-3: Pin Name PIC18F4220/4320 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Type Type PDIP TQFP QFN Description PORTE is a bidirectional I/O port. RE0/AN5/RD RE0 AN5 RD 8 RE1/AN6/WR RE1 AN6 WR 9 RE2/AN7/CS RE2 AN7 CS 10 RE3 1 VSS 12, 31 VDD NC 25 26 27 18 I/O I I ST Analog TTL Digital I/O. Analog input 5. Read control for Parallel Slave Port (see also WR and CS pins). I/O I I ST Analog TTL Digital I/O. Analog input 6.
PIC18F2220/2320/4220/4320 2.0 OSCILLATOR CONFIGURATIONS 2.1 Oscillator Types FIGURE 2-1: C1(1) The PIC18F2X20 and PIC18F4X20 devices can be operated in ten different oscillator modes. The user can program the Configuration bits, FOSC3:FOSC0, in Configuration Register 1H to select one of these ten modes: 1. 2. 3. 4. LP XT HS HSPLL 5. RC 6. RCIO 7. INTIO1 8. INTIO2 9. EC 10. ECIO 2.
PIC18F2220/2320/4220/4320 Osc Type LP XT HS CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR Crystal Freq Typical Capacitor Values Tested: C1 C2 32 kHz 33 pF 33 pF 200 kHz 15 pF 15 pF 1 MHz 33 pF 33 pF 4 MHz 27 pF 27 pF 4 MHz 27 pF 27 pF 8 MHz 22 pF 22 pF 20 MHz 15 pF 15 pF Capacitor values are for design guidance only. These capacitors were tested with the crystals listed below for basic start-up and operation. These values are not optimized.
PIC18F2220/2320/4220/4320 2.4 External Clock Input The EC and ECIO Oscillator modes require an external clock source to be connected to the OSC1 pin. There is no oscillator start-up time required after a Power-on Reset or after an exit from Sleep mode. In the EC Oscillator mode, the oscillator frequency divided by 4 is available on the OSC2 pin. This signal may be used for test purposes or to synchronize other logic. Figure 2-4 shows the pin connections for the EC Oscillator mode.
PIC18F2220/2320/4220/4320 2.6 Internal Oscillator Block The PIC18F2X20/4X20 devices include an internal oscillator block that generates two independent clock signals. Either can be used as the system’s clock source. This can eliminate the need for external oscillator circuits on the OSC1 or OSC2 pins. The main output (INTOSC) is an 8-MHz clock source that can be used to directly drive the system clock. It also drives a post-scaler that can provide a range of clock frequencies from 125 kHz to 4 MHz.
PIC18F2220/2320/4220/4320 2.6.2 OSCTUNE REGISTER The internal oscillator block is calibrated at the factory to produce an INTOSC output frequency of approximately 8 MHz. (See parameters F14–F19 in Table 26-8.) The INTOSC frequency can be adjusted using the TUN5:TUN1 bits in the OSCTUNE register OSCTUNE<5:1>. OSCTUNE<0> has no effect, but is readable and writable, enabling changes of the INTOSC frequency using two increment or decrement instructions.
PIC18F2220/2320/4220/4320 2.6.3 OSCTUN2 REGISTER The internal oscillator block is calibrated at the factory to produce an INTRC output frequency of approximately 31 kHz. (See parameters F20 and F21 in Table 26-8.) The INTRC frequency can be adjusted two ways: • If TUNSEL (OSCTUN2<7>) is clear – TUN5:TUN1 in OSCTUNE<5:1> adjusts the INTRC clock frequency and also can adjust the INTOSC clock frequency. (See Register 2-1, OSCTUNE.
PIC18F2220/2320/4220/4320 2.7 Clock Sources and Oscillator Switching Like previous PIC18 devices, the PIC18F2X20 and PIC18F4X20 devices include a feature that allows the system clock source to be switched from the main oscillator to an alternate, low-frequency clock source. PIC18F2X20/4X20 devices offer two alternate clock sources. When enabled, these give additional options for switching to the various power-managed operating modes.
PIC18F2220/2320/4220/4320 FIGURE 2-8: PIC18F2X20/4X20 CLOCK DIAGRAM PIC18F2X20/4X20 Primary Oscillator OSCCON<1:0> HSPLL 4 x PLL Sleep Clock Control CONFIG1H <3:0> OSC2 Secondary Oscillator T1OSC T1OSO OSCCON<6:4> 8 MHz OSCCON<6:4> 4 MHz Internal Oscillator Block 8 MHz (INTOSC) Postscaler INTRC Source 2 MHz 1 MHz 500 kHz 250 kHz 125 kHz 31 kHz DS39599G-page 26 Peripherals Internal Oscillator CPU 111 110 IDLEN 101 100 011 MUX T1OSI Clock Source Option for Other Modules T1OSCEN Ena
PIC18F2220/2320/4220/4320 REGISTER 2-3: OSCCON: OSCILLATOR CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R(1) R-0 R/W-0 R/W-0 IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IDLEN: Idle Enable bit 1 = Idle mode enabled; CPU core is not clocked in power-managed modes 0 = Run mode enabled; CPU core is clocked in power-manag
PIC18F2220/2320/4220/4320 2.7.2 OSCILLATOR TRANSITIONS The PIC18F2X20/4X20 devices contain circuitry to prevent clocking “glitches” when switching between clock sources. A short pause in the system clock occurs during the clock switch. The length of this pause is between 8 and 9 clock periods of the new clock source. This ensures that the new clock source is stable and that its pulse width will not be less than the shortest pulse width of the two clock sources.
PIC18F2220/2320/4220/4320 3.0 POWER-MANAGED MODES For PIC18F2X20/4X20 devices, the power-managed modes are invoked by using the existing SLEEP instruction. All modes exit to PRI_RUN mode when triggered by an interrupt, a Reset, or a WDT time-out (PRI_RUN mode is the normal full-power execution mode; the CPU and peripherals are clocked by the primary oscillator source). In addition, power-managed Run modes may also exit to Sleep mode or their corresponding Idle mode.
PIC18F2220/2320/4220/4320 3.1.2 ENTERING POWER-MANAGED MODES In general, entry, exit and switching between powermanaged clock sources requires clock source switching. In each case, the sequence of events is the same. Any change in the power-managed mode begins with loading the OSCCON register and executing a SLEEP instruction.
PIC18F2220/2320/4220/4320 TABLE 3-2: Power -Managed Mode COMPARISON BETWEEN POWER-MANAGED MODES CPU is Clocked by ... WDT Time-out Causes a ... Peripherals are Clocked by ... Clock During Wake-up (while primary becomes ready) Sleep Not clocked (not running) Wake-up Not clocked Any Idle mode Not clocked (not running) Wake-up Primary, Secondary or Unchanged from Idle mode INTOSC multiplexer (CPU operates as in corresponding Run mode).
PIC18F2220/2320/4220/4320 FIGURE 3-1: TIMING TRANSITION FOR ENTRY TO SLEEP MODE Q1 Q2 Q3 Q4 Q1 OSC1 CPU Clock Peripheral Clock Sleep Program Counter PC FIGURE 3-2: PC + 2 TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 TOST(1) PLL Clock Output TPLL(1) CPU Clock Peripheral Clock Program Counter PC Wake-up Event PC + 2 PC + 4 PC + 6 PC + 8 OSTS bit Set Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
PIC18F2220/2320/4220/4320 3.3.1 PRI_IDLE MODE This mode is unique among the three low-power Idle modes in that it does not disable the primary system clock. For timing sensitive applications, this allows for the fastest resumption of device operation, with its more accurate primary clock source, since the clock source does not have to “warm up” or transition from another oscillator. When a wake-up event occurs, the CPU is clocked from the primary clock source.
PIC18F2220/2320/4220/4320 3.3.2 SEC_IDLE MODE When a wake-up event occurs, the peripherals continue to be clocked from the Timer1 oscillator. After a 10 μs delay following the wake-up event, the CPU begins executing code, being clocked by the Timer1 oscillator. The microcontroller operates in SEC_RUN mode until the primary clock becomes ready. When the primary clock becomes ready, a clock switch back to the primary clock occurs (see Figure 3-6).
PIC18F2220/2320/4220/4320 3.3.3 RC_IDLE MODE was executed and the INTOSC source was already stable, the IOFS bit will remain set. If the IRCF bits are all clear, the INTOSC output is not enabled and the IOFS bit will remain clear; there will be no indication of the current clock source. In RC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the internal oscillator block using the INTOSC multiplexer. This mode allows for controllable power conservation during Idle periods.
PIC18F2220/2320/4220/4320 3.4 Run Modes SEC_RUN mode is entered by clearing the IDLEN bit, setting SCS1:SCS0 = 01 and executing a SLEEP instruction. The system clock source is switched to the Timer1 oscillator (see Figure 3-9), the primary oscillator is shut down, the T1RUN bit (T1CON<6>) is set and the OSTS bit is cleared. If the IDLEN bit is clear when a SLEEP instruction is executed, the CPU and peripherals are both clocked from the source selected using the SCS1:SCS0 bits.
PIC18F2220/2320/4220/4320 3.4.3 RC_RUN MODE Note: In RC_RUN mode, the CPU and peripherals are clocked from the internal oscillator block using the INTOSC multiplexer and the primary clock is shut down. When using the INTRC source, this mode provides the best power conservation of all the Run modes while still executing code. It works well for user applications which are not highly timing sensitive or do not require high-speed clocks at all times.
PIC18F2220/2320/4220/4320 3.4.4 EXIT TO IDLE MODE An exit from a power-managed Run mode to its corresponding Idle mode is executed by setting the IDLEN bit and executing a SLEEP instruction. The CPU is halted at the beginning of the instruction following the SLEEP instruction. There are no changes to any of the clock source status bits (OSTS, IOFS or T1RUN). While the CPU is halted, the peripherals continue to be clocked from the previously selected clock source. 3.4.
PIC18F2220/2320/4220/4320 TABLE 3-3: ACTIVITY AND EXIT DELAY ON WAKE-UP FROM SLEEP MODE OR ANY IDLE MODE (BY CLOCK SOURCES) Clock in Power-Managed Mode Primary System Clock (PRI_IDLE mode) Primary System Clock LP, XT, HS EC, RC, INTRC(1) OST HSPLL OST + 2 ms (1) EC, RC, INTRC LP, XT, HS HSPLL EC, RC, INTRC(1) INTOSC(2) LP, XT, HS HSPLL INTOSC Note 1: 2: 3: 4: 5: — 5-10 μs(4) IOFS OST OSTS 5-10 μs(5) — None IOFS OST OST + 2 ms EC, RC, INTRC(1) OSTS 5-10 μs(5) OST + 2 ms (2) — IOFS I
PIC18F2220/2320/4220/4320 3.5.2 EXIT BY RESET Normally, the device is held in Reset by the Oscillator Start-up Timer (OST) until the primary clock (defined in Configuration Register 1H) becomes ready. At that time, the OSTS bit is set and the device begins executing code. Code execution can begin before the primary clock becomes ready. If either the Two-Speed Start-up (see Section 23.3 “Two-Speed Start-up”) or Fail-Safe Clock Monitor (see Section 23.
PIC18F2220/2320/4220/4320 3.6.1 EXAMPLE – USART An adjustment may be indicated when the USART begins to generate framing errors or receives data with errors while in Asynchronous mode. Framing errors indicate that the system clock frequency is too high – try decrementing the value in the OSCTUNE register to reduce the system clock frequency. Errors in data may suggest that the system clock speed is too low – increment OSCTUNE. 3.6.
PIC18F2220/2320/4220/4320 NOTES: DS39599G-page 42 © 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320 4.0 RESET The PIC18F2X20/4X20 devices differentiate between various kinds of Reset: a) b) c) d) e) f) g) h) Power-on Reset (POR) MCLR Reset while executing instructions MCLR Reset when not executing instructions Watchdog Timer (WDT) Reset (during execution) Programmable Brown-out Reset (BOR) RESET Instruction Stack Full Reset Stack Underflow Reset Most registers are unaffected by a Reset. Their status is unknown on POR and unchanged by all other Resets.
PIC18F2220/2320/4220/4320 4.1 Power-on Reset (POR) A Power-on Reset pulse is generated on-chip when VDD rise is detected. To take advantage of the POR circuitry, just tie the MCLR pin through a resistor (1k to 10 kΩ) to VDD. This will eliminate external RC components usually needed to create a Power-on Reset delay. A minimum rise rate for VDD is specified (parameter D004). For a slow rise time, see Figure 4-2. When the device starts normal operation (i.e.
PIC18F2220/2320/4220/4320 TABLE 4-1: TIME-OUT IN VARIOUS SITUATIONS Power-up(2) and Brown-out Oscillator Configuration PWRTEN = 1 Exit from Power-Managed Mode 1024 TOSC + 2 ms(2) 1024 TOSC + 2 ms(2) PWRTEN = 0 HSPLL 66 ms (1) + 1024 TOSC + 2 ms (2) HS, XT, LP 66 ms(1) + 1024 TOSC 1024 TOSC 1024 TOSC EC, ECIO 66 ms(1) — — RC, RCIO (1) 66 ms — — INTIO1, INTIO2 66 ms(1) — — Note 1: 2: 66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay.
PIC18F2220/2320/4220/4320 TABLE 4-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt TOSU 2220 2320 4220 4320 ---0 0000 ---0 0000 ---0 uuuu(3) TOSH 2220 2320 4220 4320 0000 0000 0000 0000 uuuu uuuu(3) TOSL 2220 2320 4220 4320 0000 0000 0000 0000 uuuu uuuu(3) STKPTR 2220 2320 4220 4320 uu-0 0000 00-0 0000 uu-u uuuu(3) PCLATU 2220 2320 4220 4320 ---0 0000
PIC18F2220/2320/4220/4320 TABLE 4-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt FSR1H 2220 2320 4220 4320 ---- xxxx ---- uuuu ---- uuuu FSR1L 2220 2320 4220 4320 xxxx xxxx uuuu uuuu uuuu uuuu BSR 2220 2320 4220 4320 ---- 0000 ---- 0000 ---- uuuu INDF2 2220 2320 4220 4320 N/A N/A N/A POSTINC2 2220 2320 4220 4320 N/A N/A N/A Register P
PIC18F2220/2320/4220/4320 TABLE 4-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt 2220 2320 4220 4320 xxxx xxxx uuuu uuuu uuuu uuuu ADRESL 2220 2320 4220 4320 xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 2220 2320 4220 4320 --00 0000 --00 0000 --uu uuuu Register ADRESH ADCON1 2220 2320 4220 4320 --00 0000 --00 0000 --uu uuuu ADCON2 2220 2320 4220 4
PIC18F2220/2320/4220/4320 TABLE 4-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt IPR2 2220 2320 4220 4320 11-1 1111 11-1 1111 uu-u uuuu PIR2 2220 2320 4220 4320 00-0 0000 00-0 0000 uu-u uuuu(1) PIE2 2220 2320 4220 4320 00-0 0000 00-0 0000 uu-u uuuu Register IPR1 PIR1 PIE1 2220 2320 4220 4320 1111 1111 1111 1111 uuuu uuuu 2220 2320 4220 432
PIC18F2220/2320/4220/4320 FIGURE 4-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT) VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset FIGURE 4-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 FIGURE 4-5: VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset DS39599G-page 50 ©
PIC18F2220/2320/4220/4320 FIGURE 4-6: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT) 5V VDD 0V 1V MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset FIGURE 4-7: TIME-OUT SEQUENCE ON POR W/ PLL ENABLED (MCLR TIED TO VDD) VDD MCLR Internal POR TPWRT PWRT Time-out OST Time-out TOST TPLL PLL Time-out Internal Reset Note: TOST = 1024 clock cycles. TPLL ≈ 2 ms max. First three stages of the PWRT timer. © 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320 NOTES: DS39599G-page 52 © 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320 5.0 MEMORY ORGANIZATION There are three memory types in enhanced MCU devices. These memory types are: • Program Memory • Data RAM • Data EEPROM 5.1 Program Memory Organization A 21-bit program counter is capable of addressing the 2-Mbyte program memory space. Accessing a location between the physically implemented memory and the 2-Mbyte address will cause a read of all ‘0’s (a NOP instruction).
PIC18F2220/2320/4220/4320 5.2 Return Address Stack 5.2.2 The return address stack allows any combination of up to 31 program calls and interrupts to occur. The PC (Program Counter) is pushed onto the stack when a CALL or RCALL instruction is executed or an interrupt is Acknowledged. The PC value is pulled off the stack on a RETURN, RETLW or a RETFIE instruction. PCLATU and PCLATH are not affected by any of the RETURN or CALL instructions.
PIC18F2220/2320/4220/4320 REGISTER 5-1: R/C-0 STKPTR: STACK POINTER REGISTER R/C-0 (1) STKFUL STKUNF (1) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — SP4 SP3 SP2 SP1 SP0 bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 STKFUL: Stack Full Flag bit(1) 1 = Stack became full or overflowed 0 = Stack has not become full or overflowed bit 6 STKUNF: Stack Underflow Flag bit(1
PIC18F2220/2320/4220/4320 5.3 Fast Register Stack A “fast return” option is available for interrupts. A Fast Register Stack is provided for the STATUS, WREG and BSR registers and are only one in depth. The stack is not readable or writable and is loaded with the current value of the corresponding register when the processor vectors for an interrupt. The values in the registers are then loaded back into the working registers if the RETFIE, FAST instruction is used to return from the interrupt.
PIC18F2220/2320/4220/4320 5.5 Clocking Scheme/Instruction Cycle 5.6 Instruction Flow/Pipelining An “Instruction Cycle” consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle, while decode and execute take another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g.
PIC18F2220/2320/4220/4320 5.7 Instructions in Program Memory The program memory is addressed in bytes. Instructions are stored as two bytes or four bytes in program memory. The Least Significant Byte of an instruction word is always stored in a program memory location with an even address (LSB = 0). Figure 5-5 shows an example of how instruction words are stored in the program memory.
PIC18F2220/2320/4220/4320 5.8 Look-up Tables Look-up tables are implemented two ways: • Computed GOTO • Table Reads 5.8.1 COMPUTED GOTO A computed GOTO is accomplished by adding an offset to the program counter. An example is shown in Example 5-4. A look-up table can be formed with an ADDWF PCL instruction and a group of RETLW 0xnn instructions. WREG is loaded with an offset into the table before executing a call to that table. The first instruction of the called routine is the ADDWF PCL instruction.
PIC18F2220/2320/4220/4320 FIGURE 5-6: DATA MEMORY MAP FOR PIC18F2X20/4X20 DEVICES BSR<3:0> = 0000 = 0001 Data Memory Map 00h Access RAM FFh 00h GPR Bank 0 Bank 1 000h 07Fh 080h 0FFh 100h GPR 1FFh 200h FFh Access Bank Access RAM Low = 0010 = 1110 Bank 2 to Bank 14 00h 7Fh Access RAM High 80h (SFRs) FFh Unused Read ‘00h’ When a = 0: The BSR is ignored and the Access Bank is used.
PIC18F2220/2320/4220/4320 5.9.2 SPECIAL FUNCTION REGISTERS The Special Function Registers (SFRs) are registers used by the CPU and peripheral modules for controlling the desired operation of the device. These registers are implemented as static RAM. A list of these registers is given in Table 5-1 and Table 5-2. The SFRs can be classified into two sets: those associated with the “core” function and those related to the peripheral functions.
PIC18F2220/2320/4220/4320 TABLE 5-2: File Name TOSU REGISTER FILE SUMMARY (PIC18F2220/2320/4220/4320) Bit 7 Bit 6 Bit 5 — — — Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Details on page: ---0 0000 46, 54 TOSH Top-of-Stack High Byte (TOS<15:8>) 0000 0000 46, 54 TOSL Top-of-Stack Low Byte (TOS<7:0>) 0000 0000 46, 54 Return Stack Pointer 00-0 0000 46, 55 Holding Register for PC<20:16> STKPTR STKFUL STKUNF — PCLATU — — bit 21(3) Top-of-Stack Upper Byte (TOS<20:16>) Value on POR, BOR ---0
PIC18F2220/2320/4220/4320 TABLE 5-2: File Name REGISTER FILE SUMMARY (PIC18F2220/2320/4220/4320) (CONTINUED) OSCCON IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 0000 q000 27, 47 LVDCON — — IRVST LVDEN LVDL3 LVDL2 LVDL1 LVDL0 --00 0101 47, 233 — — — — — — — SWDTEN --- ---0 47, 247 IPEN — — RI TO PD POR BOR 0--1 11q0 45, 69, 98 WDTCON Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Details on page: Bit 6 RCON Bit 5 Value on POR, BOR Bit 7 TMR1H Timer1 Register High Byte
PIC18F2220/2320/4220/4320 TABLE 5-2: File Name REGISTER FILE SUMMARY (PIC18F2220/2320/4220/4320) (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Details on page: 48, 81 EEADR EEPROM Address Register 0000 0000 EEDATA EEPROM Data Register 0000 0000 48, 84 EECON2 EEPROM Control Register 2 (not a physical register) 0000 0000 48, 72, 81 EECON1 EEPGD CFGS — FREE WRERR WREN WR RD xx-0 x000 48, 73, 82 IPR2 OSCFIP CMIP — EEIP BCLIP LVDIP TMR3IP C
PIC18F2220/2320/4220/4320 5.10 Access Bank 5.11 The Access Bank is an architectural enhancement which is very useful for C compiler code optimization. The techniques used by the C compiler may also be useful for programs written in assembly. The need for a large general purpose memory space dictates a RAM banking scheme. The data memory is partitioned into as many as sixteen banks. When using direct addressing, the BSR should be configured for the desired bank.
PIC18F2220/2320/4220/4320 5.12 Indirect Addressing, INDF and FSR Registers Indirect Addressing is a mode of addressing data memory, where the data memory address in the instruction is not fixed. An FSR register is used as a pointer to the data memory location that is to be read or written. Since this pointer is in RAM, the contents can be modified by the program. This can be useful for data tables in the data memory and for software stacks.
PIC18F2220/2320/4220/4320 FIGURE 5-8: INDIRECT ADDRESSING OPERATION RAM 0h Instruction Executed Opcode Address FFFh 12 File Address = access of an Indirect Addressing register BSR<3:0> Instruction Fetched 4 Opcode FIGURE 5-9: 12 12 8 File FSR INDIRECT ADDRESSING Indirect Addressing FSRnH:FSRnL 3 0 7 0 11 0 Location Select 0000h Data Memory(1) 0FFFh Note 1: For register file map detail, see Table 5-1. © 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320 5.13 STATUS Register The STATUS register, shown in Register 5-2, contains the arithmetic status of the ALU. The STATUS register can be the operand for any instruction as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC, C, OV or N bits, then the write to these five bits is disabled. These bits are set or cleared according to the device logic.
PIC18F2220/2320/4220/4320 5.14 RCON Register The Reset Control (RCON) register contains flag bits that allow differentiation between the sources of a device Reset. These flags include the TO, PD, POR, BOR and RI bits. This register is readable and writable. Note 1: If the BOREN Configuration bit is set (Brown-out Reset enabled), the BOR bit is ‘1’ on a Power-on Reset.
PIC18F2220/2320/4220/4320 NOTES: DS39599G-page 70 © 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320 6.0 FLASH PROGRAM MEMORY The program memory space is 16 bits wide while the data RAM space is 8 bits wide. Table reads and table writes move data between these two memory spaces through an 8-bit register (TABLAT). The Flash program memory is readable, writable and erasable during normal operation over the entire VDD range. Table read operations retrieve data from program memory and place it into TABLAT in the data RAM space.
PIC18F2220/2320/4220/4320 FIGURE 6-2: TABLE WRITE OPERATION Instruction: TBLWT* Program Memory Holding Registers Table Pointer(1) TBLPTRU TBLPTRH Table Latch (8-bit) TBLPTRL TABLAT Program Memory (TBLPTR) Note 1: Table Pointer actually points to one of eight holding registers, the address of which is determined by TBLPTRL<2:0>. The process for physically writing data to the program memory array is discussed in Section 6.5 “Writing to Flash Program Memory”. 6.
PIC18F2220/2320/4220/4320 REGISTER 6-1: EECON1: DATA EEPROM CONTROL REGISTER 1 R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD CFGS — FREE WRERR(1) WREN WR RD bit 7 bit 0 Legend: S = Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory 0 = Access data EEPROM memory bit 6 CFGS: Fl
PIC18F2220/2320/4220/4320 6.2.2 TABLAT – TABLE LATCH REGISTER 6.2.4 The Table Latch (TABLAT) is an 8-bit register mapped into the SFR space. The Table Latch register is used to hold 8-bit data during data transfers between program memory and data RAM. 6.2.3 TBLPTR is used in reads, writes and erases of the Flash program memory. When a TBLRD is executed, all 22 bits of the Table Pointer determine which byte is read from program or configuration memory into TABLAT.
PIC18F2220/2320/4220/4320 6.3 Reading the Flash Program Memory The TBLRD instruction is used to retrieve data from program memory and place it into data RAM. Table reads from program memory are performed one byte at a time. The internal program memory is typically organized by words. The Least Significant bit of the address selects between the high and low bytes of the word. Figure 6-4 shows the interface between the internal program memory and the TABLAT.
PIC18F2220/2320/4220/4320 6.4 Erasing Flash Program Memory 6.4.1 The minimum erase block size is 32 words or 64 bytes under firmware control. Only through the use of an external programmer, or through ICSP control, can larger blocks of program memory be bulk erased. Word erase in Flash memory is not supported. FLASH PROGRAM MEMORY ERASE SEQUENCE The sequence of events for erasing a block of internal program memory location is: 1.
PIC18F2220/2320/4220/4320 6.5 Writing to Flash Program Memory The programming block size is 4 words or 8 bytes. Word or byte programming is not supported. Table writes are used internally to load the holding registers needed to program the Flash memory. There are 8 holding registers used by the table writes for programming. FIGURE 6-5: Since the Table Latch (TABLAT) is only a single byte, the TBLWT instruction has to be executed 8 times for each programming operation.
PIC18F2220/2320/4220/4320 EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF D'64 COUNTER BUFFER_ADDR_HIGH FSR0H BUFFER_ADDR_LOW FSR0L CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL ; number of bytes in erase block TBLRD*+ MOVFW MOVWF DECFSZ GOTO TABLAT POSTINC0 COUNTER READ_BLOCK MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF DATA_ADDR_HIGH FSR0H DATA_ADDR_LOW FSR0L NEW_DATA_LOW POSTINC0 NEW_DATA_HIGH INDF0 ; p
PIC18F2220/2320/4220/4320 EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED) PROGRAM_MEMORY BCF MOVLW MOVWF MOVLW MOVWF BSF NOP BSF DECFSZ GOTO BCF 6.5.2 INTCON,GIE 55h EECON2 AAh EECON2 EECON1,WR ; disable interrupts ; required sequence ; write 55H INTCON,GIE COUNTER_HI PROGRAM_LOOP EECON1,WREN ; re-enable interrupts ; loop until done ; write AAH ; start program (CPU stall) ; disable write to memory 6.
PIC18F2220/2320/4220/4320 NOTES: DS39599G-page 80 © 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320 7.0 DATA EEPROM MEMORY The data EEPROM is readable and writable during normal operation over the entire VDD range. The data memory is not directly mapped in the register file space. Instead, it is indirectly addressed through the Special Function Registers (SFR). There are four SFRs used to read and write the program and data EEPROM memory. These registers are: • • • • EECON1 EECON2 EEDATA EEADR The EEPROM data memory allows byte read and write.
PIC18F2220/2320/4220/4320 REGISTER 7-1: EECON1: DATA EEPROM CONTROL REGISTER 1 R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD CFGS — FREE WRERR(1) WREN WR RD bit 7 bit 0 Legend: S = Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory 0 = Access data EEPROM memory bit 6 CFGS: Fl
PIC18F2220/2320/4220/4320 7.3 Reading the Data EEPROM Memory To read a data memory location, the user must write the address to the EEADR register, clear the EEPGD control bit (EECON1<7>) and then set control bit, RD (EECON1<0>). The data is available for the very next instruction cycle; therefore, the EEDATA register can be read by the next instruction. EEDATA will hold this value until another read operation or until it is written to by the user (during a write operation). 7.
PIC18F2220/2320/4220/4320 7.7 Operation During Code-Protect 7.8 Data EEPROM memory has its own code-protect bits in Configuration Words. External read and write operations are disabled if either of these mechanisms are enabled. Using the Data EEPROM The data EEPROM is a high-endurance, byte addressable array that has been optimized for the storage of frequently changing information (e.g., program variables or other data that are updated often).
PIC18F2220/2320/4220/4320 8.0 8 X 8 HARDWARE MULTIPLIER 8.1 Introduction 8.2 Example 8-1 shows the sequence to do an 8 x 8 unsigned multiply. Only one instruction is required when one argument of the multiply is already loaded in the WREG register. An 8 x 8 hardware multiplier is included in the ALU of the PIC18F2X20/4X20 devices. By making the multiply a hardware operation, it completes in a single instruction cycle. This is an unsigned multiply that gives a 16-bit result.
PIC18F2220/2320/4220/4320 Example 8-3 shows the sequence to do a 16 x 16 unsigned multiply. Equation 8-1 shows the algorithm that is used. The 32-bit result is stored in four registers, RES3:RES0.
PIC18F2220/2320/4220/4320 9.0 INTERRUPTS The PIC18F2320/4320 devices have multiple interrupt sources and an interrupt priority feature that allows each interrupt source to be assigned a high-priority level or a low-priority level. The high-priority interrupt vector is at 000008h and the low-priority interrupt vector is at 000018h. High-priority interrupt events will interrupt any low-priority interrupts that may be in progress. There are ten registers which are used to control interrupt operation.
PIC18F2220/2320/4220/4320 FIGURE 9-1: INTERRUPT LOGIC TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT0IF INT0IE INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP PSPIF PSPIE PSPIP Wake-up if in Power-Managed Mode Interrupt to CPU Vector to Location 0008h GIE/GIEH ADIF ADIE ADIP IPE IPEN RCIF RCIE RCIP PEIE/GIEL IPEN Additional Peripheral Interrupts High-Priority Interrupt Generation Low-Priority Interrupt Generation PSPIF PSPIE PSPIP ADIF ADIE ADIP RBIF RBIE RBIP RCIF RCIE RCIP PEIE/GIEL INT0IF INT0IE Addi
PIC18F2220/2320/4220/4320 9.1 INTCON Registers Note: The INTCON registers are readable and writable registers which contain various enable, priority and flag bits. REGISTER 9-1: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling.
PIC18F2220/2320/4220/4320 REGISTER 9-2: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-1 R/W-1 INTEDG0 RBPU R/W-1 INTEDG1 R/W-1 U-0 INTEDG2 — R/W-1 U-0 R/W-1 TMR0IP — RBIP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6 INTEDG0: External Interrupt 0 E
PIC18F2220/2320/4220/4320 REGISTER 9-3: INTCON3: INTERRUPT CONTROL REGISTER 3 R/W-1 R/W-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 INT2IP: INT2 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 INT1IP: INT1 External Interrupt Priority bit 1 = High priority 0 = Low priorit
PIC18F2220/2320/4220/4320 9.2 PIR Registers The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Flag registers (PIR1, PIR2). REGISTER 9-4: Note 1: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>).
PIC18F2220/2320/4220/4320 REGISTER 9-5: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OSCFIF CMIF — EEIF BCLIF LVDIF TMR3IF CCP2IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSCFIF: Oscillator Fail Interrupt Flag bit 1 = System oscillator failed, clock input has changed to INTOSC (must be cleared in sof
PIC18F2220/2320/4220/4320 9.3 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Enable registers (PIE1, PIE2). When IPEN = 0, the PEIE bit must be set to enable any of these peripheral interrupts.
PIC18F2220/2320/4220/4320 REGISTER 9-7: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OSCFIE CMIE — EEIE BCLIE LVDIE TMR3IE CCP2IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 CMIE: Comparator Interrupt Enable bit 1 = Enabled 0 = Disabled bit 5 Unimpleme
PIC18F2220/2320/4220/4320 9.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Priority registers (IPR1, IPR2). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set.
PIC18F2220/2320/4220/4320 REGISTER 9-9: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 R/W-1 R/W-1 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 OSCFIP CMIP — EEIP BCLIP LVDIP TMR3IP CCP2IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSCFIP: Oscillator Fail Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 CMIP: Comparator Interrupt Priority bit 1 = High priority 0 = Low
PIC18F2220/2320/4220/4320 9.5 RCON Register The RCON register contains bits used to determine the cause of the last Reset or wake-up from powermanaged mode. RCON also contains the bit that enables interrupt priorities (IPEN).
PIC18F2220/2320/4220/4320 9.6 INTx Pin Interrupts 9.8 External interrupts on the RB0/INT0, RB1/INT1 and RB2/INT2 pins are edge triggered: either rising if the corresponding INTEDGx bit is set in the INTCON2 register, or falling if the INTEDGx bit is clear. When a valid edge appears on the RBx/INTx pin, the corresponding flag bit, INTxIF, is set. This interrupt can be disabled by clearing the corresponding enable bit, INTxIE.
PIC18F2220/2320/4220/4320 NOTES: DS39599G-page 100 © 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320 10.0 I/O PORTS 10.1 Depending on the device selected and features enabled, there are up to five ports available. Some pins of the I/O ports are multiplexed with an alternate function from the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Each port has three registers for its operation.
PIC18F2220/2320/4220/4320 FIGURE 10-2: BLOCK DIAGRAM OF RA3:RA0 AND RA5 PINS FIGURE 10-4: BLOCK DIAGRAM OF RA4/T0CKI PIN RD LATA RD LATA Data Bus WR LATA or PORTA D Data Bus WR LATA or PORTA Q VDD CK Q P Data Latch WR TRISA Analog Input Mode D Q CK Q D Q CK Q I/O pin(1) N Data Latch N I/O pin(1) WR TRISA VSS D Q CK Q VSS Schmitt Trigger Input Buffer TRIS Latch TRIS Latch RD TRISA RD TRISA Q TTL Input Buffer D Q ENEN EN RD PORTA RD PORTA SS Input (RA5 only) TMR0 Clock
PIC18F2220/2320/4220/4320 TABLE 10-1: PORTA FUNCTIONS Name RA0/AN0 Bit# Buffer bit 0 TTL Function Input/output or analog input. RA1/AN1 bit 1 TTL Input/output or analog input. RA2/AN2/VREF-/CVREF bit 2 TTL Input/output, analog input, VREF- or comparator VREF output. RA3/AN3/VREF+ bit 3 TTL Input/output, analog input or VREF+. RA4/T0CKI/C1OUT bit 4 ST Input/output, external clock input for Timer0 or Comparator 1 output. Output is open-drain type.
PIC18F2220/2320/4220/4320 10.2 PORTB, TRISB and LATB Registers PORTB is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., put the contents of the output latch on the selected pin). The Data Latch register (LATB) is also memory mapped.
PIC18F2220/2320/4220/4320 FIGURE 10-7: BLOCK DIAGRAM OF RB2:RB0 PINS RBPU(2) Weak P Pull-up D D WR LATB or PORTB I/O pin I/O pin(1) CK WR TRISB Q CK TRIS Latch D Q Data Latch D Weak P Pull-up Data Latch Data Bus Q (1) WR LATB or PORTB BLOCK DIAGRAM OF RB4 PIN VDD VDD RBPU(2) Analog Input Mode Data Bus FIGURE 10-8: Q WR TRISB CK TTL Input Buffer TRIS Latch TTL Input Buffer CK RD TRISB RD TRISB RD LATB Latch RD LATB Q Q D RD PORTB D EN Set RBIF ENEN Q1 RD PORTB INTx Q
PIC18F2220/2320/4220/4320 TABLE 10-3: PORTB FUNCTIONS Name Bit# Buffer RB0/AN12/INT0 bit 0 TTL(1)/ST(2) Input/output pin, analog input or external interrupt input 0. Internal software programmable weak pull-up. RB1/AN10/INT1 bit 1 TTL(1)/ST(2) Input/output pin, analog input or external interrupt input 1. Internal software programmable weak pull-up. RB2/AN8/INT2 bit 2 TTL(1)/ST(2) Input/output pin, analog input or external interrupt input 2. Internal software programmable weak pull-up.
PIC18F2220/2320/4220/4320 10.3 PORTC, TRISC and LATC Registers Note: PORTC is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISC. Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., put the contents of the output latch on the selected pin). The Data Latch register (LATC) is also memory mapped.
PIC18F2220/2320/4220/4320 TABLE 10-5: PORTC FUNCTIONS Name Bit# Buffer Type Function RC0/T1OSO/T1CKI bit 0 ST Input/output port pin or Timer1 oscillator output/Timer1 clock input. RC1/T1OSI/CCP2 bit 1 ST Input/output port pin, Timer1 oscillator input or Capture 2 input/ Compare 2 output/PWM output when CCP2MX Configuration bit is disabled. RC2/CCP1/P1A(1) bit 2 ST Input/output port pin, Capture 1 input/Compare 1 output/PWM1 output or Enhanced PWM output A(1).
PIC18F2220/2320/4220/4320 10.4 Note: PORTD, TRISD and LATD Registers PORTD can also be configured as an 8-bit wide microprocessor port (Parallel Slave Port) by setting control bit, PSPMODE (TRISE<4>). In this mode, the input buffers are TTL. See Section 10.6 “Parallel Slave Port” for additional information on the Parallel Slave Port (PSP). PORTD is only available on PIC18F4X20 devices. PORTD is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISD.
PIC18F2220/2320/4220/4320 FIGURE 10-12: BLOCK DIAGRAM OF RD4:RD0 PINS PORTD/CCP1 Select PSPMODE RD LATD Data Bus D Q CK Q WR LATD or PORTD VDD P Data Latch D Q CK Q I/O pin(1) WR TRISD 0 N TRIS Latch PSP Read VSS 1 TTL Buffer RD TRISD 1 Q D 0 RD PORTD PSP Write Note 1: TABLE 10-7: ENEN 0 Schmitt Trigger Input Buffer 1 I/O pins have diode protection to VDD and VSS. PORTD FUNCTIONS Name Bit# Buffer Type bit 0 ST/TTL(1) Input/output port pin or Parallel Slave Port bit 0.
PIC18F2220/2320/4220/4320 10.5 PORTE, TRISE and LATE Registers PORTE is available only in PIC18F4X20 devices. PIC18F2X20 devices always will read back 0x00 from PORTE. For PIC18F4X20 devices, PORTE is a 4-bit wide port. Three pins (RE0/AN5/RD, RE1/AN6/WR and RE2/ AN7/CS) are individually configurable as inputs or outputs. These pins have Schmitt Trigger input buffers. When selected as an analog input, these pins will read as ‘0’s. The corresponding Data Direction register is TRISE.
PIC18F2220/2320/4220/4320 FIGURE 10-14: BLOCK DIAGRAM OF MCLR/VPP/RE3 PIN MCLRE Data Bus MCLR/VPP/ RE3 RD TRISE Schmitt Trigger RD LATE Latch Q D EN RD PORTE High-Voltage Detect HV Internal MCLR Filter Low-Level MCLR Detect REGISTER 10-1: TRISE REGISTER R-0 R-0 R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1 IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is c
PIC18F2220/2320/4220/4320 TABLE 10-9: PORTE FUNCTIONS Name Bit# Buffer Type Function RE0/AN5/RD bit 0 ST/TTL(1) Input/output port pin, analog input or read control input in Parallel Slave Port mode. For RD (PSP Control mode): 1 = PSP is Idle 0 = Read operation. Reads PORTD register (if chip selected). RE1/AN6/WR bit 1 ST/TTL(1) Input/output port pin, analog input or write control input in Parallel Slave Port mode. For WR (PSP Control mode): 1 = PSP is Idle 0 = Write operation.
PIC18F2220/2320/4220/4320 10.6 Note: Parallel Slave Port The Parallel Slave Port is only available on PIC18F4X20 devices. In addition to its function as a general I/O port, PORTD can also operate as an 8-bit wide Parallel Slave Port (PSP) or microprocessor port. PSP operation is controlled by the 4 upper bits of the TRISE register (Register 10-1). Setting control bit, PSPMODE (TRISE<4>), enables PSP operation, as long as the Enhanced CCP module is not operating in dual output or quad output PWM mode.
PIC18F2220/2320/4220/4320 FIGURE 10-16: PARALLEL SLAVE PORT WRITE WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF FIGURE 10-17: PARALLEL SLAVE PORT READ WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF TABLE 10-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets PORTD Port Data Latch when written; Port pins when
PIC18F2220/2320/4220/4320 NOTES: DS39599G-page 116 © 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320 11.0 TIMER0 MODULE Figure 11-1 shows a simplified block diagram of the Timer0 module in 8-bit mode and Figure 11-2 shows a simplified block diagram of the Timer0 module in 16-bit mode.
PIC18F2220/2320/4220/4320 FIGURE 11-1: TIMER0 BLOCK DIAGRAM IN 8-BIT MODE Data Bus RA4/T0CKI/C1OUT pin FOSC/4 0 0 1 Programmable Prescaler 1 8 Sync with Internal Clocks TMR0 (2 TCY delay) T0SE 3 PSA Set Interrupt Flag bit TMR0IF on Overflow T0PS2, T0PS1, T0PS0 T0CS Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI maximum prescale.
PIC18F2220/2320/4220/4320 11.1 Timer0 Operation 11.2.1 Timer0 can operate as a timer or as a counter. The prescaler assignment is fully under software control (i.e., it can be changed “on-the-fly” during program execution). Timer mode is selected by clearing the T0CS bit. In Timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If the TMR0 register is written, the increment is inhibited for the following two instruction cycles.
PIC18F2220/2320/4220/4320 NOTES: DS39599G-page 120 © 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320 12.0 TIMER1 MODULE The Timer1 module timer/counter has the following features: • 16-bit timer/counter (two 8-bit registers: TMR1H and TMR1L) • Readable and writable (both registers) • Internal or external clock select • Interrupt-on-overflow from FFFFh to 0000h • Reset from CCP module Special Event Trigger • Status of system clock operation Figure 12-1 is a simplified block diagram of the Timer1 module. REGISTER 12-1: Register 12-1 details the Timer1 Control register.
PIC18F2220/2320/4220/4320 12.1 Timer1 Operation When TMR1CS = 0, Timer1 increments every instruction cycle. When TMR1CS = 1, Timer1 increments on every rising edge of the external clock input, or the Timer1 oscillator, if enabled. Timer1 can operate in one of these modes: • As a timer • As a synchronous counter • As an asynchronous counter When the Timer1 oscillator is enabled (T1OSCEN is set), the RC1/T1OSI/CCP2 and RC0/T1OSO/T1CKI pins become inputs.
PIC18F2220/2320/4220/4320 12.2 Timer1 Oscillator 12.3 A crystal oscillator circuit is built-in between pins, T1OSI (input) and T1OSO (amplifier output). It is enabled by setting control bit, T1OSCEN (T1CON<3>). The oscillator is a low-power oscillator rated for 32 kHz crystals. It will continue to run during all powermanaged modes. The circuit for a typical LP oscillator is shown in Figure 12-3. Table 12-1 shows the capacitor selection for the Timer1 oscillator.
PIC18F2220/2320/4220/4320 12.4 Timer1 Interrupt The TMR1 register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The Timer1 interrupt, if enabled, is generated on overflow which is latched in interrupt flag bit, TMR1IF (PIR1<0>). This interrupt can be enabled/disabled by setting/clearing Timer1 interrupt enable bit, TMR1IE (PIE1<0>). 12.
PIC18F2220/2320/4220/4320 EXAMPLE 12-1: IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE RTCinit MOVLW MOVWF CLRF MOVLW MOVWF CLRF CLRF MOVLW MOVWF BSF RETURN 0x80 TMR1H TMR1L b’00001111’ T1OSC secs mins .12 hours PIE1, TMR1IE BSF BCF INCF MOVLW CPFSGT RETURN CLRF INCF MOVLW CPFSGT RETURN CLRF INCF MOVLW CPFSGT RETURN MOVLW MOVWF RETURN TMR1H,7 PIR1,TMR1IF secs,F .
PIC18F2220/2320/4220/4320 NOTES: DS39599G-page 126 © 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320 13.0 TIMER2 MODULE 13.1 The Timer2 module timer has the following features: • • • • • • • 8-bit Timer register (TMR2) 8-bit Period register (PR2) Readable and writable (both registers) Software programmable prescaler (1:1, 1:4, 1:16) Software programmable postscaler (1:1 to 1:16) Interrupt on TMR2 match with PR2 MSSP module optional use of TMR2 output to generate clock shift Timer2 has a control register shown in Register 13-1.
PIC18F2220/2320/4220/4320 13.2 Timer2 Interrupt 13.3 The Timer2 module has an 8-bit Period register, PR2. Timer2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle. PR2 is a readable and writable register. The PR2 register is initialized to FFh upon Reset. FIGURE 13-1: Output of TMR2 The output of TMR2 (before the postscaler) is fed to the Synchronous Serial Port module which optionally uses it to generate the shift clock.
PIC18F2220/2320/4220/4320 14.0 TIMER3 MODULE The Timer3 module timer/counter has the following features: • 16-bit timer/counter (two 8-bit registers: TMR3H and TMR3L) • Readable and writable (both registers) • Internal or external clock select • Interrupt-on-overflow from FFFFh to 0000h • Reset from CCP module trigger REGISTER 14-1: Figure 14-1 is a simplified block diagram of the Timer3 module. Register 14-1 shows the Timer3 Control register.
PIC18F2220/2320/4220/4320 14.1 Timer3 Operation When TMR3CS = 0, Timer3 increments every instruction cycle. When TMR3CS = 1, Timer3 increments on every rising edge of the Timer1 external clock input or the Timer1 oscillator if enabled. Timer3 can operate in one of these modes: • As a timer • As a synchronous counter • As an asynchronous counter When the Timer1 oscillator is enabled (T1OSCEN is set), the RC1/T1OSI/CCP2 and RC0/T1OSO/T1CKI pins become inputs.
PIC18F2220/2320/4220/4320 14.2 Timer1 Oscillator 14.4 The Timer1 oscillator may be used as the clock source for Timer3. The Timer1 oscillator is enabled by setting the T1OSCEN (T1CON<3>) bit. The oscillator is a lowpower oscillator rated for 32 kHz crystals. See Section 12.2 “Timer1 Oscillator” for further details. 14.3 Timer3 Interrupt TABLE 14-1: If the CCP module is configured in Compare mode to generate a “Special Event Trigger” (CCP1M3:CCP1M0 = 1011), this signal will reset Timer3.
PIC18F2220/2320/4220/4320 NOTES: DS39599G-page 132 © 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320 15.0 CAPTURE/COMPARE/PWM (CCP) MODULES Note: The standard CCP (Capture/Compare/PWM) module contains a 16-bit register that can operate as a 16-bit Capture register, a 16-bit Compare register or a PWM Master/Slave Duty Cycle register. Table 15-1 shows the timer resources required for each of the CCP module modes. Please see Section 16.0 “Enhanced Capture/Compare/PWM (ECCP) Module” for a discussion of the enhanced PWM capabilities of the CCP1 module.
PIC18F2220/2320/4220/4320 15.1 CCP1 Module 15.2 CCP2 Module Capture/Compare/PWM Register 1 (CCPR1) is comprised of two 8-bit registers: CCPR1L (low byte) and CCPR1H (high byte). The CCP1CON register controls the operation of CCP1. All are readable and writable. Capture/Compare/PWM Register 2 (CCPR2) is comprised of two 8-bit registers: CCPR2L (low byte) and CCPR2H (high byte). The CCP2CON register controls the operation of CCP2. All are readable and writable.
PIC18F2220/2320/4220/4320 15.3 Capture Mode 15.3.3 In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 or TMR3 registers when an event occurs on pin RC2/CCP1/P1A. An event is defined as one of the following: • • • • every falling edge every rising edge every 4th rising edge every 16th rising edge 15.3.1 CCP PIN CONFIGURATION In Capture mode, the RC2/CCP1/P1A pin should be configured as an input by setting the TRISC<2> bit. Note: 15.3.
PIC18F2220/2320/4220/4320 15.4 Compare Mode 15.4.2 Timer1 and/or Timer3 must be running in Timer mode, or Synchronized Counter mode, if the CCP module is using the compare feature. In Asynchronous Counter mode, the compare operation may not work. In Compare mode, the 16-bit CCPR1 (CCPR2) register value is constantly compared against either the TMR1 register pair value, or the TMR3 register pair value. When a match occurs, the RC2/CCP1/P1A (RC1/T1OSI/CCP2) pin: • • • • 15.4.
PIC18F2220/2320/4220/4320 TABLE 15-3: Name REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Value on all other Resets Bit 0 Value on POR, BOR RBIF 0000 000x 0000 000u INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP (1) ADIP RCIP TXIP SSPI
PIC18F2220/2320/4220/4320 15.5 PWM Mode 15.5.1 In Pulse Width Modulation (PWM) mode, the CCP1 pin produces up to a 10-bit resolution PWM output. Since the CCP1 pin is multiplexed with the PORTC data latch, the TRISC<2> bit must be cleared to make the CCP1 pin an output. Note: Clearing the CCP1CON register will force the CCP1 PWM output latch to the default low level. This is not the PORTC I/O data latch. Figure 15-3 shows a simplified block diagram of the CCP module in PWM mode.
PIC18F2220/2320/4220/4320 The CCPR1H register and a 2-bit internal latch are used to double-buffer the PWM duty cycle. This double-buffering is essential for glitchless PWM operation. When the CCPR1H and 2-bit latch match TMR2, concatenated with an internal 2-bit Q clock or two bits of the TMR2 prescaler, the CCP1 pin is cleared. The maximum PWM resolution (bits) for a given PWM frequency is given by the following equation. 15.5.3 EQUATION 15-3: 4.
PIC18F2220/2320/4220/4320 NOTES: DS39599G-page 140 © 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320 16.0 ENHANCED CAPTURE/ COMPARE/PWM (ECCP) MODULE Note: The ECCP (Enhanced Capture/ Compare/ PWM) module is only available on PIC18F4X20 devices. In 40 and 44-pin devices, the CCP1 module is implemented as a standard CCP module with enhanced PWM capabilities. Operation of the Capture, Compare and standard single output PWM modes is described in Section 15.0 “Capture/Compare/PWM (CCP) Modules”.
PIC18F2220/2320/4220/4320 REGISTER 16-1: bit 3-0 CCP1CON: ECCP CONTROL REGISTER (40/44-PIN DEVICES) (CONTINUED) CCP1M3:CCP1M0: ECCP Mode Select bits 0000 = Capture/Compare/PWM off (resets ECCP module) 0001 = Unused (reserved) 0010 = Compare mode, toggle output on match (CCP1IF bit is set) 0011 = Unused (reserved) 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode, set outp
PIC18F2220/2320/4220/4320 16.4 Enhanced PWM Mode waveforms do not exactly match the standard PWM waveforms but are instead offset by one full instruction cycle (4 TOSC). The Enhanced PWM mode provides additional PWM output options for a broader range of control applications. The module is an upwardly compatible version of the standard CCP module and offers up to four outputs, designated P1A through P1D. Users are also able to select the polarity of the signal (either active-high or active-low).
PIC18F2220/2320/4220/4320 FIGURE 16-2: PWM OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE) SIGNAL CCP1CON <7:6> 00 0 PR2+1 Duty Cycle Period (Single Output) P1A Modulated Delay(1) Delay(1) P1A Modulated 10 (Half-Bridge) P1B Modulated P1A Active 01 P1B Inactive (Full-Bridge, Forward) P1C Inactive P1D Modulated P1A Inactive 11 P1B Modulated (Full-Bridge, Reverse) P1C Active P1D Inactive FIGURE 16-3: PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE) CCP1CON <7:6> 00 (Single Output) SIGNAL 0 Peri
PIC18F2220/2320/4220/4320 16.4.2 HALF-BRIDGE MODE FIGURE 16-4: In the Half-Bridge Output mode, two pins are used as outputs to drive push-pull loads. The PWM output signal is output on the RC2/CCP1/P1A pin, while the complementary PWM output signal is output on the RD5/ PSP5/P1B pin (Figure 16-4). This mode can be used for half-bridge applications, as shown in Figure 16-5, or for full-bridge applications where four power switches are being modulated with two PWM signals.
PIC18F2220/2320/4220/4320 16.4.3 FULL-BRIDGE MODE In Full-Bridge Output mode, four pins are used as outputs; however, only two outputs are active at a time. In the Forward mode, pin RC2/CCP1/P1A is continuously active and pin RD7/PSP7/P1D is modulated. In the Reverse mode, RD6/PSP6/P1C pin is continuously active and RD5/PSP5/P1B pin is modulated. These are illustrated in Figure 16-6. FIGURE 16-6: P1A, P1B, P1C and P1D outputs are multiplexed with the PORTC<2> and PORTD<5:7> data latches.
PIC18F2220/2320/4220/4320 FIGURE 16-7: EXAMPLE OF FULL-BRIDGE APPLICATION V+ PIC18F4220/4320 FET Driver QC QA FET Driver P1A Load P1B FET Driver P1C FET Driver QD QB VP1D 16.4.3.1 Direction Change in Full-Bridge Mode In the Full-Bridge Output mode, the P1M1 bit in the CCP1CON register allows users to control the forward/ reverse direction. When the application firmware changes this direction control bit, the module will assume the new direction on the next PWM cycle.
PIC18F2220/2320/4220/4320 FIGURE 16-8: PWM DIRECTION CHANGE Period(1) SIGNAL Period P1A (Active High) P1B (Active High) DC P1C (Active High) (Note 2) P1D (Active High) DC Note 1: The direction bit in the CCP1 Control register (CCP1CON<7>) is written any time during the PWM cycle. 2: When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle at intervals of 4 TOSC, 16 TOSC or 64 TOSC, depending on the Timer2 prescaler value.
PIC18F2220/2320/4220/4320 16.4.4 PROGRAMMABLE DEAD-BAND DELAY In half-bridge applications, where all power switches are modulated at the PWM frequency at all times, the power switches normally require more time to turn off than to turn on. If both the upper and lower power switches are switched at the same time (one turned on and the other turned off), both switches may be on for a short period of time until one switch completely turns off.
PIC18F2220/2320/4220/4320 REGISTER 16-3: ECCPAS: ENHANCED CAPTURE/COMPARE/PWM AUTO-SHUTDOWN CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ECCPASE: ECCP Auto-Shutdown Event Status bit 1 = A shutdown event has occurred; ECCP outputs are
PIC18F2220/2320/4220/4320 16.4.5.1 Auto-Shutdown and Automatic Restart The auto-shutdown feature can be configured to allow automatic restarts of the module following a shutdown event. This is enabled by setting the PRSEN bit of the PWM1CON register (PWM1CON<7>). In Shutdown mode with PRSEN = 1 (Figure 16-10), the ECCPASE bit will remain set for as long as the cause of the shutdown continues. When the shutdown condition clears, the ECCPASE bit is cleared.
PIC18F2220/2320/4220/4320 16.4.7 SETUP FOR PWM OPERATION The following steps should be taken when configuring the ECCP module for PWM operation: 1. 2. 3. 4. 5. 6. 7. 8. 9. Configure the PWM pins P1A and P1B (and P1C and P1D, if used) as inputs by setting the corresponding TRISC and TRISD bits. Set the PWM period by loading the PR2 register.
PIC18F2220/2320/4220/4320 TABLE 16-2: Name INTCON RCON REGISTERS ASSOCIATED WITH ENHANCED PWM AND TIMER2 Bit 7 Bit 6 GIE/GIEH PEIE/GIEL IPEN — Value on all other Resets Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u — RI TO PD POR BOR 0--1 11q0 0--q qquu PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
PIC18F2220/2320/4220/4320 NOTES: DS39599G-page 154 © 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320 17.0 17.1 MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE Master SSP (MSSP) Module Overview The Master Synchronous Serial Port (MSSP) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc.
PIC18F2220/2320/4220/4320 17.3.1 REGISTERS SSPSR is the shift register used for shifting data in or out. SSPBUF is the buffer register to which data bytes are written to or read from. The MSSP module has four registers for SPI mode operation. These are: • • • • In receive operations, SSPSR and SSPBUF together create a double-buffered receiver. When SSPSR receives a complete byte, it is transferred to SSPBUF and the SSPIF interrupt is set.
PIC18F2220/2320/4220/4320 REGISTER 17-2: SSPCON1: MSSP CONTROL REGISTER 1 (SPI MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV(1) SSPEN(2) CKP SSPM3(3) SSPM2(3) SSPM1(3) SSPM0(3) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit (Transmit mode only) 1 = The SSPBUF register is written while it is still transmittin
PIC18F2220/2320/4220/4320 17.3.2 OPERATION When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPCON1<5:0> and SSPSTAT<7:6>).
PIC18F2220/2320/4220/4320 17.3.3 ENABLING SPI I/O 17.3.4 To enable the serial port, MSSP Enable bit, SSPEN (SSPCON1<5>), must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, re-initialize the SSPCON registers and then set the SSPEN bit. This configures the SDI, SDO, SCK and SS pins as serial port pins. For the pins to behave as the serial port function, some must have their data direction bits (in the TRIS register) appropriately programmed.
PIC18F2220/2320/4220/4320 17.3.5 MASTER MODE The master can initiate the data transfer at any time because it controls the SCK. The master determines when the slave (Processor 2, Figure 17-2) is to broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPBUF register is written to. If the SPI is only going to receive, the SDO output could be disabled (programmed as an input).
PIC18F2220/2320/4220/4320 17.3.6 SLAVE MODE In Slave mode, the data is transmitted and received as the external clock pulses appear on SCK. When the last bit is latched, the SSPIF interrupt flag bit is set. While in Slave mode, the external clock is supplied by the external clock source on the SCK pin. This external clock must meet the minimum high and low times as specified in the electrical specifications. While in power-managed modes, the slave can transmit/receive data.
PIC18F2220/2320/4220/4320 FIGURE 17-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO SDI (SMP = 0) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 0 bit 7 Input Sample (SMP = 0) SSPIF Interrupt Flag Next Q4 Cycle after Q2↓ SSPSR to SSPBUF FIGURE 17-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPBUF SDO SDI (SMP = 0) bit 7 bit 7 bit 6 bit
PIC18F2220/2320/4220/4320 17.3.8 MASTER IN POWER-MANAGED MODES 17.3.8.1 Slave in Power-Managed Modes In Slave mode, the SPI Transmit/Receive Shift register operates asynchronously to the device. This allows the device to be placed in any power-managed mode and data to be shifted into the SPI Transmit/Receive Shift register. When all 8 bits have been received, the MSSP interrupt flag bit will be set and if MSSP interrupts are enabled, will wake the device from a power-managed mode.
PIC18F2220/2320/4220/4320 17.4 I2C Mode 17.4.1 The MSSP module in I 2C mode fully implements all master and slave functions (including general call support) and provides interrupts on Start and Stop bits in hardware to determine a free bus (multi-master function). The MSSP module implements the standard mode specifications, as well as 7-bit and 10-bit addressing.
PIC18F2220/2320/4220/4320 REGISTER 17-3: SSPSTAT: MSSP STATUS REGISTER (I2C™ MODE) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P(1) S(2) R/W UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SMP: Slew Rate Control bit In Master or Slave mode: 1 = Slew rate control disabled 0 = Slew rate control enabled bit 6 CKE: SMBus Select bit In Master or Slave m
PIC18F2220/2320/4220/4320 REGISTER 17-4: R/W-0 SSPCON1: MSSP CONTROL REGISTER 1 (I2C™ MODE) R/W-0 WCOL SSPOV R/W-0 SSPEN (1) R/W-0 CKP R/W-0 SSPM3 (2) R/W-0 SSPM2 (2) R/W-0 SSPM1 (2) R/W-0 SSPM0(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit In Master Transmit mode: 1 = A write to the SSPBUF register was attempted while the I2C
PIC18F2220/2320/4220/4320 REGISTER 17-5: SSPCON2: MSSP CONTROL REGISTER 2 (I2C™ MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GCEN ACKSTAT ACKDT(1) ACKEN RCEN PEN RSEN SEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GCEN: General Call Enable bit (Slave mode only) 1 = Enable interrupt when a general call address (0000h) is received in the SSPSR 0 =
PIC18F2220/2320/4220/4320 17.4.2 OPERATION The MSSP module functions are enabled by setting MSSP Enable bit, SSPEN (SSPCON1<5>). The SSPCON1 register allows control of the I 2C operation.
PIC18F2220/2320/4220/4320 17.4.3.2 Reception When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the SSPSTAT register is cleared. The received address is loaded into the SSPBUF register and the SDA line is held low (ACK). When the address byte overflow condition exists, then the no Acknowledge (ACK) pulse is given. An overflow condition is defined as either bit, BF (SSPSTAT<0>), is set or bit, SSPOV (SSPCON1<6>), is set.
DS39599G-page 170 CKP 2 A6 3 4 A4 5 A3 Receiving Address A5 6 A2 (CKP does not reset to ‘0’ when SEN = 0) SSPOV (SSPCON1<6>) BF (SSPSTAT<0>) SSPIF (PIR1<3>) 1 SCL S A7 7 A1 8 9 ACK R/W = 0 1 D7 3 4 D4 5 D3 Receiving Data D5 Cleared in software SSPBUF is read 2 D6 6 D2 7 D1 8 D0 9 ACK 1 D7 2 D6 3 4 D4 5 D3 Receiving Data D5 6 D2 7 D1 8 D0 Bus master terminates transfer P SSPOV is set because SSPBUF is still full. ACK is not sent.
© 2007 Microchip Technology Inc.
DS39599G-page 172 2 1 4 1 5 0 7 A8 UA is set indicating that the SSPADD needs to be updated SSPBUF is written with contents of SSPSR 6 A9 8 9 (CKP does not reset to ‘0’ when SEN = 0) UA (SSPSTAT<1>) SSPOV (SSPCON1<6>) CKP 3 1 Cleared in software BF (SSPSTAT<0>) SSPIF (PIR1<3>) 1 SCL S 1 ACK R/W = 0 A7 2 4 A4 5 A3 6 A2 8 9 A0 ACK UA is set indicating that SSPADD needs to be updated Cleared by hardware when SSPADD is updated with low byte of address 7 A1 Cleared in
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320 17.4.4 CLOCK STRETCHING Both 7 and 10-bit Slave modes implement automatic clock stretching during a transmit sequence. The SEN bit (SSPCON2<0>) allows clock stretching to be enabled during receives. Setting SEN will cause the SCL pin to be held low at the end of each data receive sequence. 17.4.4.
PIC18F2220/2320/4220/4320 17.4.4.5 Clock Synchronization and the CKP bit (SEN = 1) The SEN bit is also used to synchronize writes to the CKP bit. If a user clears the CKP bit, the SCL output is forced to ‘0’. When the SEN bit is set to ‘1’, setting the CKP bit will not assert the SCL output low until the SCL output is already sampled low. If the user attempts to drive SCL low, the CKP bit will not assert the SCL line until an external I2C master device has already asserted the SCL line.
DS39599G-page 176 CKP SSPOV (SSPCON1<6>) BF (SSPSTAT<0>) SSPIF (PIR1<3>) 1 SCL S A7 2 A6 3 4 A4 5 A3 Receiving Address A5 6 A2 7 A1 8 9 ACK R/W = 0 3 4 D4 5 D3 Receiving Data D5 Cleared in software 2 D6 If BF is cleared prior to the falling edge of the 9th clock, CKP will not be reset to ‘0’ and no clock stretching will occur SSPBUF is read 1 D7 6 D2 7 D1 9 ACK 1 D7 BF is set after falling edge of the 9th clock, CKP is reset to ‘0’ and clock stretching occurs 8
© 2007 Microchip Technology Inc. 2 1 UA (SSPSTAT<1>) SSPOV (SSPCON1<6>) CKP 3 1 4 1 5 0 6 7 A9 A8 8 UA is set indicating that the SSPADD needs to be updated SSPBUF is written with contents of SSPSR Cleared in software BF (SSPSTAT<0>) SSPIF (PIR1<3>) 1 SCL S 1 9 ACK R/W = 0 A7 2 4 5 A4 A3 6 A2 Cleared in software 3 A5 7 A1 8 A0 Note: An update of the SSPADD register before the falling edge of the ninth clock will have no effect on UA and UA will remain set.
PIC18F2220/2320/4220/4320 17.4.5 GENERAL CALL ADDRESS SUPPORT If the general call address matches, the SSPSR is transferred to the SSPBUF, the BF flag bit is set (eighth bit) and on the falling edge of the ninth bit (ACK bit), the SSPIF interrupt flag bit is set. The addressing procedure for the I2C bus is such that the first byte after the Start condition usually determines which device will be the slave addressed by the master. The exception is the general call address, which can address all devices.
PIC18F2220/2320/4220/4320 MASTER MODE Note: Master mode is enabled by setting and clearing the appropriate SSPM bits in SSPCON1 and by setting the SSPEN bit. In Master mode, the SCL and SDA lines are manipulated by the MSSP hardware. Master mode of operation is supported by interrupt generation on the detection of the Start and Stop conditions. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP module is disabled.
PIC18F2220/2320/4220/4320 17.4.6.1 I2C Master Mode Operation The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended with a Stop condition or with a Repeated Start condition. Since the Repeated Start condition is also the beginning of the next serial transfer, the I2C bus will not be released. In Master Transmitter mode, serial data is output through SDA, while SCL outputs the serial clock.
PIC18F2220/2320/4220/4320 17.4.7 BAUD RATE 17.4.7.1 2 In I C Master mode, the Baud Rate Generator (BRG) reload value is placed in the lower 7 bits of the SSPADD register (Register 17-17). When a write occurs to SSPBUF, the Baud Rate Generator will automatically begin counting. The BRG counts down to ‘0’ and stops until another reload has taken place. The BRG count is decremented twice per instruction cycle (TCY) on the Q2 and Q4 clocks. In I2C Master mode, the BRG is reloaded automatically.
PIC18F2220/2320/4220/4320 17.4.7.2 Clock Arbitration Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, deasserts the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the FIGURE 17-18: SCL pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<6:0> and begins counting.
PIC18F2220/2320/4220/4320 17.4.8 I2C MASTER MODE START CONDITION TIMING 17.4.8.1 If the user writes the SSPBUF when a Start sequence is in progress, the WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). To initiate a Start condition, the user sets the Start Condition Enable bit, SEN (SSPCON2<0>). If the SDA and SCL pins are sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<6:0> and starts its count.
PIC18F2220/2320/4220/4320 17.4.9 I2C MASTER MODE REPEATED START CONDITION TIMING Immediately following the SSPIF bit getting set, the user may write the SSPBUF with the 7-bit address in 7-bit mode, or the default first address in 10-bit mode. After the first eight bits are transmitted and an ACK is received, the user may then transmit an additional eight bits of address (10-bit mode) or eight bits of data (7-bit mode).
PIC18F2220/2320/4220/4320 17.4.10 I2C MASTER MODE TRANSMISSION Transmission of a data byte, a 7-bit address or the other half of a 10-bit address is accomplished by simply writing a value to the SSPBUF register. This action will set the Buffer Full Flag bit, BF, and allow the Baud Rate Generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDA pin after the falling edge of SCL is asserted (see data hold time specification parameter #106).
DS39599G-page 186 S R/W PEN SEN BF (SSPSTAT<0>) SSPIF SCL SDA A6 A5 A4 A3 A2 A1 3 4 5 Cleared in software 2 6 7 8 9 After Start condition, SEN cleared by hardware SSPBUF written 1 D7 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 SSPBUF is written in software Cleared in software service routine from MSSP interrupt 2 D6 Transmitting Data or Second Half of 10-bit Address 1 SCL held low while CPU responds to SSPIF ACK = 0 R/W = 0 SSPBUF written with 7-bit address and R/W, start tra
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320 17.4.12 ACKNOWLEDGE SEQUENCE TIMING 17.4.13 An Acknowledge sequence is enabled by setting the Acknowledge Sequence Enable bit, ACKEN (SSPCON2<4>). When this bit is set, the SCL pin is pulled low and the contents of the Acknowledge data bit are presented on the SDA pin. If the user wishes to generate an Acknowledge, then the ACKDT bit should be cleared. If not, the user should set the ACKDT bit before starting an Acknowledge sequence.
PIC18F2220/2320/4220/4320 17.4.14 POWER-MANAGED MODE OPERATION 17.4.17 While in any power-managed mode, the I2C module can receive addresses or data and when an address match or complete byte transfer occurs, wake the processor from Sleep (if the MSSP interrupt is enabled). 17.4.15 EFFECT OF A RESET A Reset disables the MSSP module and terminates the current transfer. 17.4.
PIC18F2220/2320/4220/4320 17.4.17.1 Bus Collision During a Start Condition During a Start condition, a bus collision occurs if: a) b) SDA or SCL is sampled low at the beginning of the Start condition (Figure 17-26). SCL is sampled low before SDA is asserted low (Figure 17-27). During a Start condition, both the SDA and the SCL pins are monitored. If the SDA pin is sampled low during this count, the BRG is reset and the SDA line is asserted early (Figure 17-28).
PIC18F2220/2320/4220/4320 FIGURE 17-27: BUS COLLISION DURING START CONDITION (SCL = 0) SDA = 0, SCL = 1 TBRG TBRG SDA Set SEN, enable Start sequence if SDA = 1, SCL = 1 SCL SCL = 0 before SDA = 0, bus collision occurs. Set BCLIF. SEN SCL = 0 before BRG time-out, bus collision occurs. Set BCLIF.
PIC18F2220/2320/4220/4320 17.4.17.2 Bus Collision During a Repeated Start Condition If SDA is low, a bus collision has occurred (i.e., another master is attempting to transmit a data ‘0’, Figure 17-29). If SDA is sampled high, the BRG is reloaded and begins counting. If SDA goes from high-to-low before the BRG times out, no bus collision occurs because no two masters can assert SDA at exactly the same time.
PIC18F2220/2320/4220/4320 17.4.17.3 Bus Collision During a Stop Condition The Stop condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPADD<6:0> and counts down to 0. After the BRG times out, SDA is sampled. If SDA is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data ‘0’ (Register 17-31).
PIC18F2220/2320/4220/4320 NOTES: DS39599G-page 194 © 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320 18.0 ADDRESSABLE UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (USART) The Universal Synchronous Asynchronous Receiver Transmitter (USART) module is one of the two serial I/O modules available in the PIC18F2X20/4X20 family of microcontrollers. (USART is also known as a Serial Communications Interface or SCI.
PIC18F2220/2320/4220/4320 REGISTER 18-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R-1 R/W-0 CSRC TX9 TXEN(1) SYNC — BRGH TRMT TX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care.
PIC18F2220/2320/4220/4320 REGISTER 18-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins) 0 = Serial port disabled (held in Reset)
PIC18F2220/2320/4220/4320 18.2 USART Baud Rate Generator (BRG) The BRG supports both the Asynchronous and Synchronous modes of the USART. It is a dedicated 8-bit Baud Rate Generator. The SPBRG register controls the period of a free-running 8-bit timer. In Asynchronous mode, bit BRGH (TXSTA<2>) also controls the baud rate. In Synchronous mode, bit BRGH is ignored. Table 18-1 shows the formula for computation of the baud rate for different USART modes which only apply in Master mode (internal clock).
PIC18F2220/2320/4220/4320 TABLE 18-3: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0, LOW SPEED) FOSC = 40.000 MHz BAUD RATE (K) FOSC = 20.000 MHz Actual Rate (K) % Error 0.3 — — — — — 1.2 — — — 1.22 1.73 2.4 2.44 1.73 255 2.40 0.16 9.6 9.62 0.16 64 9.47 -1.36 19.2 18.94 -1.36 32 19.53 1.73 15 38.4 39.06 1.73 15 39.06 1.73 7 57.6 56.82 -1.36 10 62.50 8.51 4 76.8 78.13 1.73 7 78.13 1.73 3 SPBRG value (decimal) Actual Rate (K) % Error FOSC = 16.
PIC18F2220/2320/4220/4320 TABLE 18-4: BAUD RATE (K) BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1, HIGH SPEED) FOSC = 40.000 MHz Actual Rate (K) % Error SPBRG value (decimal) FOSC = 20.000 MHz Actual Rate (K) % Error SPBRG value (decimal) FOSC = 16.000 MHz Actual Rate (K) % Error FOSC = 10.000 MHz SPBRG value (decimal) Actual Rate (K) % Error SPBRG value (decimal) 2.4 — — — 4.88 103.45 255 3.91 62.76 255 2.44 1.73 255 9.6 9.77 1.73 255 9.62 0.16 129 9.62 0.16 103 9.63 0.
PIC18F2220/2320/4220/4320 TABLE 18-5: BAUD RATE (K) BAUD RATES FOR SYNCHRONOUS MODE (SYNC = 1) FOSC = 40.000 MHz Actual Rate (K) % Error SPBRG value (decimal) FOSC = 20.000 MHz Actual Rate (K) % Error SPBRG value (decimal) FOSC = 16.000 MHz Actual Rate (K) % Error SPBRG value (decimal) FOSC = 10.000 MHz Actual Rate (K) % Error SPBRG value (decimal) 9.6 — — — — — — 15.63 62.76 255 9.77 1.73 255 19.2 — — — 19.53 1.73 255 19.23 0.16 207 19.23 0.16 129 38.4 39.06 1.
PIC18F2220/2320/4220/4320 18.3 USART Asynchronous Mode 18.3.1 In this mode, the USART uses standard Non-Returnto-Zero (NRZ) format (one Start bit, eight or nine data bits and one Stop bit). The most common data format is 8 bits. An on-chip dedicated 8-bit Baud Rate Generator can be used to derive standard baud rate frequencies from the oscillator. The USART transmits and receives the LSb first. The USART’s transmitter and receiver are functionally independent but use the same data format and baud rate.
PIC18F2220/2320/4220/4320 FIGURE 18-2: ASYNCHRONOUS TRANSMISSION Write to TXREG Word 1 BRG Output (Shift Clock) RC6/TX/CK (pin) Start bit bit 0 bit 1 bit 7/8 Stop bit Word 1 TXIF bit (Transmit Buffer Reg. Empty Flag) 1 TCY Word 1 Transmit Shift Reg TRMT bit (Transmit Shift Reg. Empty Flag) FIGURE 18-3: ASYNCHRONOUS TRANSMISSION (BACK TO BACK) Write to TXREG Word 2 Word 1 BRG Output (Shift Clock) RC6/TX/CK (pin) TXIF bit (Interrupt Reg.
PIC18F2220/2320/4220/4320 18.3.2 USART ASYNCHRONOUS RECEIVER 18.3.3 The receiver block diagram is shown in Figure 18-4. The data is received on the RC7/RX/DT pin and drives the data recovery block. The data recovery block is actually a high-speed shifter, operating at x16 times the baud rate, whereas the main receive serial shifter operates at the bit rate or at FOSC. This mode would typically be used in RS-232 systems. This mode would typically be used in RS-485 systems.
PIC18F2220/2320/4220/4320 To set up an Asynchronous Transmission: 1. 2. 3. 4. 5. Initialize the SPBRG register for the appropriate baud rate. If a high-speed baud rate is desired, set bit BRGH (Section 18.2 “USART Baud Rate Generator (BRG)”). Enable the asynchronous serial port by clearing bit, SYNC, and setting bit, SPEN. If interrupts are desired, set enable bit, TXIE. If 9-bit transmission is desired, set Transmit bit, TX9. Can be used as address/data bit. FIGURE 18-5: 6. 7. 8.
PIC18F2220/2320/4220/4320 18.4 USART Synchronous Master Mode (PIE1<4>). Flag bit, TXIF, will be set regardless of the state of enable bit, TXIE, and cannot be cleared in software. It will reset only when new data is loaded into the TXREG register. While flag bit, TXIF, indicates the status of the TXREG register, another bit, TRMT (TXSTA<1>), shows the status of the TSR register. TRMT is a read-only bit which is set when the TSR is empty.
PIC18F2220/2320/4220/4320 FIGURE 18-7: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RC7/RX/DT pin bit 0 bit 2 bit 1 bit 6 bit 7 RC6/TX/CK pin Write to TXREG reg TXIF bit TRMT bit TXEN bit TABLE 18-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Name Bit 7 Bit 6 INTCON GIE/ GIEH PEIE/ GIEL Bit 5 Bit 4 TMR0IE INT0IE Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF
PIC18F2220/2320/4220/4320 18.4.2 USART SYNCHRONOUS MASTER RECEPTION Once Synchronous mode is selected, reception is enabled by setting either enable bit, SREN (RCSTA<5>), or enable bit, CREN (RCSTA<4>). Data is sampled on the RC7/RX/DT pin on the falling edge of the clock. If enable bit, SREN, is set, only a single word is received. If enable bit, CREN, is set, the reception is continuous until CREN is cleared. If both bits are set, then CREN takes precedence. To set up a Synchronous Master Reception: 1.
PIC18F2220/2320/4220/4320 18.5 USART Synchronous Slave Mode To set up a Synchronous Slave Transmission: Synchronous Slave mode differs from the Master mode in the fact that the shift clock is supplied externally at the RC6/TX/CK pin (instead of being supplied internally in Master mode). This allows the device to transfer or receive data while in any power-managed mode. Slave mode is entered by clearing bit, CSRC (TXSTA<7>). 18.5.
PIC18F2220/2320/4220/4320 18.5.2 USART SYNCHRONOUS SLAVE RECEPTION To set up a Synchronous Slave Reception: 1. The operation of the Synchronous Master and Slave modes is identical, except in the case of Sleep or any Idle mode and bit, SREN, which is a “don’t care” in Slave mode. 2. 3. 4. 5. If receive is enabled by setting bit, CREN, prior to entering Sleep or any Idle mode, then a word may be received while in this power-managed mode.
PIC18F2220/2320/4220/4320 19.0 10-BIT ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE The Analog-to-Digital (A/D) converter module has 10 inputs for the PIC18F2X20 devices and 13 for the PIC18F4X20 devices. This module allows conversion of an analog input signal to a corresponding 10-bit digital number. A new feature for the A/D converter is the addition of programmable acquisition time. This feature allows the user to select a new channel for conversion and setting the GO/DONE bit immediately.
PIC18F2220/2320/4220/4320 REGISTER 19-2: ADCON1: A/D CONTROL REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-0(1) R/W(1) R/W(1) R/W(1) — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared PCFG3: PCFG0 AN6(2) AN5(2) AN4 AN3 AN2 AN1 AN0 PCFG3:PCFG0: A/D Port Configuration Control bits: AN7(2) bit 3-0 AN8 VCFG0: Voltage Reference Configuration bit (VREF+ so
PIC18F2220/2320/4220/4320 REGISTER 19-3: ADCON2: A/D CONTROL REGISTER 2 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ADFM: A/D Result Format Select bit 1 = Right justified 0 = Left justified bit 6 Unimplemented: Read as ‘0’ bit 5-3 ACQT2:ACQT0: A/D Acquisition Time Select bits 111 = 20
PIC18F2220/2320/4220/4320 The analog reference voltage is software selectable to either the device’s positive and negative supply voltage (AVDD and AVSS), or the voltage level on the RA3/AN3/ VREF+ and RA2/AN2/VREF-/CVREF pins. A device Reset forces all registers to their Reset state. This forces the A/D module to be turned off and any conversion in progress is aborted. Each port pin associated with the A/D converter can be configured as an analog input or as a digital I/O.
PIC18F2220/2320/4220/4320 The value in the ADRESH/ADRESL registers is not modified for a Power-on Reset. The ADRESH/ ADRESL registers will contain unknown data after a Power-on Reset. 2. After the A/D module has been configured as desired, the selected channel must be acquired before the conversion is started. The analog input channels must have their corresponding TRIS bits selected as an input. To determine acquisition time, see Section 19.1 “A/D Acquisition Requirements”.
PIC18F2220/2320/4220/4320 19.1 A/D Acquisition Requirements For the A/D converter to meet its specified accuracy, the Charge Holding Capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 19-2. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD).
PIC18F2220/2320/4220/4320 19.3 Selecting and Configuring Automatic Acquisition Time 19.4 Selecting the A/D Conversion Clock The ADCON2 register allows the user to select an acquisition time that occurs each time the GO/DONE bit is set. The A/D conversion time per bit is defined as TAD. The A/D conversion requires 11 TAD per 10-bit conversion. The source of the A/D conversion clock is software selectable.
PIC18F2220/2320/4220/4320 19.5 Operation in Power-Managed Modes The selection of the automatic acquisition time and A/D conversion clock is determined in part by the clock source and frequency while in a power-managed mode. If the A/D is expected to operate while the device is in a power-managed mode, the ACQT2:ACQT0 and ADCS2:ADCS0 bits in ADCON2 should be updated in accordance with the power-managed mode clock that will be used.
PIC18F2220/2320/4220/4320 19.7 A/D Conversions Figure 19-3 shows the operation of the A/D converter after the GO/DONE bit has been set and the ACQT2:ACQT0 bits are cleared. A conversion is started after the following instruction to allow entry into Sleep mode before the conversion begins. Clearing the GO/DONE bit during a conversion will abort the current conversion. The A/D Result register pair will NOT be updated with the partially completed A/D conversion sample.
PIC18F2220/2320/4220/4320 19.8 Use of the CCP2 Trigger desired location). The appropriate analog input channel must be selected and the minimum acquisition period is either timed by the user or an appropriate TACQ time, selected before the “Special Event Trigger”, sets the GO/DONE bit (starts a conversion). An A/D conversion can be started by the “Special Event Trigger” of the CCP2 module.
PIC18F2220/2320/4220/4320 20.0 COMPARATOR MODULE 20.1 The comparator module contains two analog comparators. The inputs and outputs for the comparators are multiplexed with the RA0 through RA5 pins. The onchip voltage reference (Section 21.0 “Comparator Voltage Reference Module”) can also be an input to the comparators. The CMCON register, shown as Register 20-1, controls the comparator module’s input and output multiplexers.
PIC18F2220/2320/4220/4320 FIGURE 20-1: COMPARATOR I/O OPERATING MODES Comparators RESET CM<2:0> = 000 D VIN- RA3/AN3/ D VREF+ VIN+ D VIN- RA2/AN2/ D VREF-/CVREF VIN+ RA0/AN0 RA1/AN1 Comparators Off (POR Default Value) CM<2:0> = 111 C1 Off (Read as ‘0’) A VIN- RA3/AN3/ A VREF+ VIN+ A VIN- RA2/AN2/ A VREF-/CVREF VIN+ RA1/AN1 VIN- RA3/AN3/ D VREF+ VIN+ D VIN- RA2/AN2/ D VREF-/CVREF VIN+ RA1/AN1 C2 Off (Read as ‘0’) RA0/AN0 C1 C1 Off (Read as ‘0’) C2 Off (Read as ‘0’) Two In
PIC18F2220/2320/4220/4320 20.2 Comparator Operation 20.3.2 INTERNAL REFERENCE SIGNAL A single comparator is shown in Figure 20-2, along with the relationship between the analog input levels and the digital output. When the analog input at VIN+ is less than the analog input VIN-, the output of the comparator is a digital low level. When the analog input at VIN+ is greater than the analog input VIN-, the output of the comparator is a digital high level.
PIC18F2220/2320/4220/4320 FIGURE 20-3: COMPARATOR OUTPUT BLOCK DIAGRAM Port Pins MULTIPLEX + CxINV To RA4 or RA5 Pin Bus Data Q Read CMCON Set CMIF bit D EN Q From Other Comparator D EN CL Read CMCON Reset 20.6 Comparator Interrupts The comparator interrupt flag is set whenever there is a change in the output value of either comparator. Software will need to maintain information about the status of the output bits, as read from CMCON<7:6>, to determine the actual change that occurred.
PIC18F2220/2320/4220/4320 20.7 Comparator Operation in Power-Managed Modes 20.9 When a comparator is active and the device is placed in a power-managed mode, the comparator remains active and the interrupt is functional if enabled. This interrupt will wake-up the device from a powermanaged mode when enabled. Each operational comparator will consume additional current, as shown in the comparator specifications.
PIC18F2220/2320/4220/4320 TABLE 20-1: Name REGISTERS ASSOCIATED WITH COMPARATOR MODULE Value on POR Value on all other Resets Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0111 0000 0111 CVRCON CVREN CVROE CVRR — CVR3 CVR2 CVR1 CVR0 000- 0000 000- 0000 INTCON GIE/ GIEH PEIE/ GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 0000 0000 0000 PIR2 OSCFIF CMIF — EEIF BCLIF LVDIF TMR3IF CCP2IF 00-0 0000 00-0 0000
PIC18F2220/2320/4220/4320 21.0 COMPARATOR VOLTAGE REFERENCE MODULE 21.1 The comparator voltage reference is a 16-tap resistor ladder network that provides a selectable voltage reference. The resistor ladder is segmented to provide two ranges of CVREF values and has a power-down function to conserve power when the reference is not being used. The CVRCON register controls the operation of the reference as shown in Register 21-1. The block diagram is given in Figure 21-1.
PIC18F2220/2320/4220/4320 FIGURE 21-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM VDD 16 Stages CVREN 8R R R R R CVRR RA2/AN2/VREF-/CVREF 8R CVROE CVREF 21.2 Voltage Reference Accuracy/Error The full range of voltage reference cannot be realized due to the construction of the module. The transistors on the top and bottom of the resistor ladder network (Figure 21-1) keep CVREF from approaching the reference source rails.
PIC18F2220/2320/4220/4320 FIGURE 21-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE R(1) CVREF Module RA2 + – CVREF Output Voltage Reference Output Impedance Note 1: R is dependent upon the voltage reference configuration bits (CVRCON<3:0> and CVRCON<5>).
PIC18F2220/2320/4220/4320 NOTES: DS39599G-page 230 © 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320 22.0 LOW-VOLTAGE DETECT In many applications, the ability to determine if the device voltage (VDD) is below a specified voltage level is a desirable feature. A window of operation for the application can be created, where the application software can do “housekeeping tasks” before the device voltage exits the valid operating range. This can be done using the Low-Voltage Detect (LVD) module.
PIC18F2220/2320/4220/4320 FIGURE 22-2: LOW-VOLTAGE DETECT (LVD) BLOCK DIAGRAM LVDIN LVD Control Register 16-to-1 MUX VDD Internally Generated Reference Voltage 1.2V LVDEN The LVD module has an additional feature that allows the user to supply the sense voltage to the module from an external source. This mode is enabled when bits LVDL3:LVDL0 are set to ‘1111’. In this state, the comparator input is multiplexed from the external input FIGURE 22-3: LVDIF pin, LVDIN (Figure 22-3).
PIC18F2220/2320/4220/4320 22.1 Control Register The Low-Voltage Detect Control register controls the operation of the Low-Voltage Detect circuitry.
PIC18F2220/2320/4220/4320 22.2 Operation The following steps are needed to set up the LVD module: Depending on the power source for the device voltage, the voltage normally decreases relatively slowly. This means that the LVD module does not need to be constantly operating. To decrease the current requirements, the LVD circuitry only needs to be enabled for short periods where the voltage is checked. After doing the check, the LVD module may be disabled. 1. 2. 3.
PIC18F2220/2320/4220/4320 22.2.1 REFERENCE VOLTAGE SET POINT The internal reference voltage of the LVD module may be used by other internal circuitry (the Programmable Brown-out Reset). If these circuits are disabled (lower current consumption), the reference voltage circuit requires a time to become stable before a low-voltage condition can be reliably detected. This time is invariant of system clock speed. This start-up time is specified in electrical specification parameter #36.
PIC18F2220/2320/4220/4320 NOTES: DS39599G-page 236 © 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320 23.0 SPECIAL FEATURES OF THE CPU The inclusion of an internal RC oscillator also provides the additional benefits of a Fail-Safe Clock Monitor (FSCM) and Two-Speed Start-up. FSCM provides for background monitoring of the peripheral clock and automatic switchover in the event of its failure. TwoSpeed Start-up enables code to be executed almost immediately on start-up while the primary clock source completes its start-up delays.
PIC18F2220/2320/4220/4320 REGISTER 23-1: CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h) R/P-1 R/P-1 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 IESO FSCM — — FOSC3 FOSC2 FOSC1 FOSC0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ u = Unchanged from programmed state bit 7 IESO: Internal/External Switchover bit 1 = Internal/External Switchover mode enabled 0 = Internal/External Switchover mode disa
PIC18F2220/2320/4220/4320 REGISTER 23-2: U-0 CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h) U-0 — — U-0 — U-0 — R/P-1 BORV1 R/P-1 BORV0 R/P-1 (1) BOR bit 7 R/P-1 PWRTEN(1) bit 0 Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ u = Unchanged from programmed state bit 7-4 Unimplemented: Read as ‘0’ bit 3-2 BORV1:BORV0: Brown-out Reset Voltage bits 11 = VBOR set to 2.0V 10 = VBOR set to 2.
PIC18F2220/2320/4220/4320 REGISTER 23-3: U-0 CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h) U-0 — — U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 — WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN bit 7 bit 0 Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ u = Unchanged from programmed state bit 7-5 Unimplemented: Read as ‘0’ bit 4-1 WDPS<3:0>: Watchdog Timer Postscale Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8
PIC18F2220/2320/4220/4320 REGISTER 23-4: CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h) R/P-1 U-0 U-0 U-0 U-0 U-0 R/P-1 R/P-1 MCLRE — — — — — PBAD CCP2MX bit 7 bit 0 Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ u = Unchanged from programmed state bit 7 MCLRE: MCLR Pin Enable bit 1 = MCLR pin enabled; RE3 input pin disabled 0 = MCLR disabled; RE3 input is enabled in 40-pin devices only (PIC18F4
PIC18F2220/2320/4220/4320 REGISTER 23-6: U-0 CONFIG5L: CONFIGURATION REGISTER 5 LOW (BYTE ADDRESS 300008h) U-0 — — U-0 — U-0 — R/C-1 R/C-1 (1) (1) CP3 CP2 R/C-1 R/C-1 CP1 CP0 bit 7 bit 0 Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state bit 7-4 Unimplemented: Read as ‘0’ bit 3 CP3: Code Protection bit(1) 1 = Block 3 (001800-001FFFh) not code-protected 0 = Block 3 (001800-001FFFh)
PIC18F2220/2320/4220/4320 REGISTER 23-8: CONFIG6L: CONFIGURATION REGISTER 6 LOW (BYTE ADDRESS 30000Ah) U-0 U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 — — — — WRT3(1) WRT2(1) WRT1 WRT0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ u = Unchanged from programmed state bit 7-4 Unimplemented: Read as ‘0’ bit 3 WRT3: Write Protection bit(1) 1 = Block 3 (001800-001FFFh) not write-protected 0 = Block 3 (001800-
PIC18F2220/2320/4220/4320 REGISTER 23-10: CONFIG7L: CONFIGURATION REGISTER 7 LOW (BYTE ADDRESS 30000Ch) U-0 U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 — — — — EBTR3(1) EBTR2(1) EBTR1 EBTR0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ u = Unchanged from programmed state bit 7-4 Unimplemented: Read as ‘0’ bit 3 EBTR3: Table Read Protection bit(1) 1 = Block 3 (001800-001FFFh) not protected from table reads
PIC18F2220/2320/4220/4320 REGISTER 23-12: DEVID1: DEVICE ID REGISTER 1 FOR PIC18F2220/2320/4220/4320 DEVICES R R R R R R R R DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 bit 7 bit 0 Legend: R = Read-only bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ u = Unchanged from programmed state bit 7-5 DEV2:DEV0: Device ID bits 000 = PIC18F2320 001 = PIC18F4320 100 = PIC18F2220 101 = PIC18F4220 bit 4-0 REV3:REV0: Revision ID bits These bits are
PIC18F2220/2320/4220/4320 23.2 Watchdog Timer (WDT) For PIC18F2X20/4X20 devices, the WDT is driven by the INTRC source. When the WDT is enabled, the clock source is also enabled. The nominal WDT period is 4 ms and has the same stability as the INTRC oscillator. The 4 ms period of the WDT is multiplied by a 16-bit postscaler. Any output of the WDT postscaler is selected by a multiplexer, controlled by bits in Configuration Register 2H. Available periods range from 4 ms to 131.072 seconds (2.18 minutes).
PIC18F2220/2320/4220/4320 REGISTER 23-14: WDTCON: WATCHDOG TIMER CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — SWDTEN(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-1 Unimplemented: Read as ‘0’ bit 0 SWDTEN: Software Controlled Watchdog Timer Enable bit(1) 1 = Watchdog Timer is on 0 = Watchdog Timer is off Note 1: This bit has no effect if the Configurati
PIC18F2220/2320/4220/4320 23.3 Two-Speed Start-up Reset. For wake-ups from Sleep, the INTOSC or postscaler clock sources can be selected by setting IFRC2:IFRC0 prior to entering Sleep mode. The Two-Speed Start-up feature helps to minimize the latency period from oscillator start-up to code execution by allowing the microcontroller to use the INTRC oscillator as a clock source until the primary clock source is available. It is enabled by setting the IESO bit in Configuration Register 1H (CONFIG1H<7>).
PIC18F2220/2320/4220/4320 23.4 Fail-Safe Clock Monitor The Fail-Safe Clock Monitor (FSCM) allows the microcontroller to continue operation, in the event of an external oscillator failure, by automatically switching the system clock to the internal oscillator block. The FSCM function is enabled by setting the Fail-Safe Clock Monitor Enable bit, FCMEN (CONFIG1H<6>).
PIC18F2220/2320/4220/4320 23.4.2 EXITING FAIL-SAFE OPERATION The fail-safe condition is terminated by either a device Reset or by entering a power-managed mode. On Reset, the controller starts the primary clock source specified in Configuration Register 1H (with any required start-up delays that are required for the oscillator mode, such as OST or PLL timer). The INTOSC multiplexer provides the system clock until the primary clock source becomes ready (similar to a Two-speed Start-up).
PIC18F2220/2320/4220/4320 23.4.3 FSCM INTERRUPTS IN POWER-MANAGED MODES As previously mentioned, entering a power-managed mode clears the fail-safe condition. By entering a power-managed mode, the clock multiplexer selects the clock source selected by the OSCCON register. Fail-safe monitoring of the power-managed clock source resumes in the power-managed mode.
PIC18F2220/2320/4220/4320 23.5 Program Verification and Code Protection Each of the five blocks has three code protection bits associated with them. They are: The overall structure of the code protection on the PIC18 Flash devices differs significantly from other PIC® devices. • Code-Protect bit (CPn) • Write-Protect bit (WRTn) • External Block Table Read bit (EBTRn) The user program memory is divided into five blocks. One of these is a boot block of 512 bytes.
PIC18F2220/2320/4220/4320 23.5.1 PROGRAM MEMORY CODE PROTECTION The program memory may be read to or written from any location using the table read and table write instructions. The Device ID may be read with table reads. The Configuration registers may be read and written with the table read and table write instructions. A table read instruction that executes from a location outside of that block is not allowed to read and will result in reading ‘0’s.
PIC18F2220/2320/4220/4320 FIGURE 23-7: EXTERNAL BLOCK TABLE READ (EBTRx) DISALLOWED Register Values Program Memory Configuration Bit Settings 000000h 0001FFh 000200h TBLPTR = 0002FFh PC = 000FFEh WRTB, EBTRB = 11 WRT0, EBTR0 = 10 TBLRD * 0007FFh 000800h 000FFFh 001000h WRT1, EBTR1 = 11 WRT2, EBTR2 = 11 0017FFh 001800h WRT3, EBTR3 = 11 001FFFh Results: All table reads from external blocks to Blockn are disabled whenever EBTRx = 0. TABLAT register returns a value of ‘0’.
PIC18F2220/2320/4220/4320 23.5.2 DATA EEPROM CODE PROTECTION The entire data EEPROM is protected from external reads and writes by two bits: CPD and WRTD. CPD inhibits external reads and writes of data EEPROM. WRTD inhibits external writes to data EEPROM. The CPU can continue to read and write data EEPROM regardless of the protection bit settings. 23.5.3 CONFIGURATION REGISTER PROTECTION The Configuration registers can be write-protected. The WRTC bit controls protection of the Configuration registers.
PIC18F2220/2320/4220/4320 NOTES: DS39599G-page 256 © 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320 24.0 INSTRUCTION SET SUMMARY The PIC18 instruction set adds many enhancements to the previous PIC MCU instruction sets, while maintaining an easy migration from these PIC MCU instruction sets. Most instructions are a single program memory word (16 bits) but there are three instructions that require two program memory locations.
PIC18F2220/2320/4220/4320 TABLE 24-1: OPCODE FIELD DESCRIPTIONS Field Description a RAM access bit: a = 0: RAM location in Access RAM (BSR register is ignored) a = 1: RAM bank is specified by BSR register bbb Bit address within an 8-bit file register (0 to 7). BSR Bank Select Register. Used to select the current RAM bank. d Destination select bit: d = 0: store result in WREG d = 1: store result in file register f dest Destination either the WREG register or the specified register file location.
PIC18F2220/2320/4220/4320 FIGURE 24-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 15 10 9 8 7 OPCODE d a Example Instruction 0 f (FILE #) ADDWF MYREG, W, B d = 0 for result destination to be WREG register d = 1 for result destination to be file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Byte to Byte move operations (2-word) 15 12 11 OPCODE 15 0 f (Source FILE #) 12 11 MOVFF MYREG1, MYREG2 0 f (Destination FILE #)
PIC18F2220/2320/4220/4320 TABLE 24-2: PIC18FXXX INSTRUCTION SET Mnemonic, Operands Description Cycles 16-Bit Instruction Word MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ADDWFC ANDWF CLRF COMF CPFSEQ CPFSGT CPFSLT DECF DECFSZ DCFSNZ INCF INCFSZ INFSNZ IORWF MOVF MOVFF f, d, a f, d, a f, d, a f, a f, d, a f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f s, f d MOVWF MULWF NEGF RLCF RLNCF RRCF RRNCF SETF SUBFWB f, a f, a f, a f, d, a f
PIC18F2220/2320/4220/4320 TABLE 24-2: PIC18FXXX INSTRUCTION SET (CONTINUED) Mnemonic, Operands Description Cycles 16-Bit Instruction Word MSb LSb Status Affected Notes CONTROL OPERATIONS BC BN BNC BNN BNOV BNZ BOV BRA BZ CALL n n n n n n n n n n, s CLRWDT DAW GOTO — — n NOP NOP POP PUSH RCALL RESET RETFIE — — — — n RETLW RETURN SLEEP 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 2 1 (2) 2 s Branch if Carry Branch if Negative Branch if Not Carry Branch if Not Negative Branch if Not Overflow Bra
PIC18F2220/2320/4220/4320 TABLE 24-2: PIC18FXXX INSTRUCTION SET (CONTINUED) Mnemonic, Operands Description Cycles 16-Bit Instruction Word MSb LSb Status Affected Notes LITERAL OPERATIONS ADDLW ANDLW IORLW LFSR k k k f, k MOVLB MOVLW MULLW RETLW SUBLW XORLW k k k k k k Add Literal and WREG AND Literal with WREG Inclusive OR Literal with WREG Move Literal (12-bit) 2nd word to FSRx 1st word Move Literal to BSR<3:0> Move Literal to WREG Multiply Literal with WREG Return with Literal in WREG Subtrac
PIC18F2220/2320/4220/4320 24.2 Instruction Set ADDLW ADD Literal to W Syntax: [ label ] ADDLW Operands: 0 ≤ k ≤ 255 Operation: (W) + k → W Status Affected: N, OV, C, DC, Z Encoding: 0000 1111 k kkkk kkkk Description: The contents of W are added to the 8-bit literal ‘k’ and the result is placed in W.
PIC18F2220/2320/4220/4320 ADDWFC ADD W and Carry bit to f ANDLW AND Literal with W Syntax: [ label ] ADDWFC Syntax: [ label ] ANDLW Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] f [,d [,a]] Operation: (W) + (f) + (C) → dest Status Affected: N, OV, C, DC, Z Encoding: 0010 Description: 1 Cycles: 1 0 ≤ k ≤ 255 Operation: (W) .AND. k → W Status Affected: N, Z Encoding: ffff ffff Add W, the Carry flag and data memory location ‘f’. If ‘d’ is ‘0’, the result is placed in W.
PIC18F2220/2320/4220/4320 ANDWF AND W with f Syntax: [ label ] ANDWF Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] f [,d [,a]] Operation: (W) .AND.
PIC18F2220/2320/4220/4320 BCF Bit Clear f Syntax: [ label ] BCF Operands: 0 ≤ f ≤ 255 0≤b≤7 a ∈ [0,1] Operation: 0 → f Status Affected: None Encoding: 1001 Description: Branch if Negative Syntax: [ label ] BN Operands: -128 ≤ n ≤ 127 Operation: if Negative bit is ‘1’, (PC) + 2 + 2n → PC Status Affected: None Encoding: bbba ffff ffff 1110 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Read register ‘f’ Process Data Write register ‘f’ Example: BCF Before Instruction FLAG_RE
PIC18F2220/2320/4220/4320 BNC Branch if Not Carry BNN Branch if Not Negative Syntax: [ label ] BNC Syntax: [ label ] BNN Operands: -128 ≤ n ≤ 127 Operands: -128 ≤ n ≤ 127 Operation: if Carry bit is ‘0’, (PC) + 2 + 2n → PC Operation: if Negative bit is ‘0’, (PC) + 2 + 2n → PC Status Affected: None Status Affected: None Encoding: 1110 n 0011 nnnn nnnn Encoding: 1110 n 0111 nnnn nnnn Description: If the Carry bit is ‘0’, then the program will branch.
PIC18F2220/2320/4220/4320 BNOV Branch if Not Overflow BNZ Branch if Not Zero Syntax: [ label ] BNOV Syntax: [ label ] BNZ Operands: -128 ≤ n ≤ 127 Operands: -128 ≤ n ≤ 127 Operation: if Overflow bit is ‘0’, (PC) + 2 + 2n → PC Operation: if Zero bit is ‘0’, (PC) + 2 + 2n → PC Status Affected: None Status Affected: None Encoding: 1110 n 0101 nnnn nnnn Encoding: 1110 n 0001 nnnn nnnn Description: If the Overflow bit is ‘0’, then the program will branch.
PIC18F2220/2320/4220/4320 BRA Unconditional Branch BSF Bit Set f Syntax: [ label ] BRA Syntax: [ label ] BSF Operands: -1024 ≤ n ≤ 1023 Operands: Operation: (PC) + 2 + 2n → PC Status Affected: None 0 ≤ f ≤ 255 0≤b≤7 a ∈ [0,1] Operation: 1 → f Status Affected: None Encoding: Description: 1101 1 Cycles: 2 Q Cycle Activity: Q1 No operation 0nnn nnnn nnnn Add the 2’s complement number ‘2n’ to the PC.
PIC18F2220/2320/4220/4320 BTFSC Bit Test File, Skip if Clear BTFSS Bit Test File, Skip if Set Syntax: [ label ] BTFSC f,b[,a] Syntax: [ label ] BTFSS f,b[,a] Operands: 0 ≤ f ≤ 255 0≤b≤7 a ∈ [0,1] Operands: 0 ≤ f ≤ 255 0≤b<7 a ∈ [0,1] Operation: skip if (f) = 0 Operation: skip if (f) = 1 Status Affected: None Status Affected: None Encoding: 1011 bbba ffff ffff Encoding: 1010 bbba ffff ffff Description: If bit ‘b’ in register ‘f’ is ‘0’, then the next instruction is skippe
PIC18F2220/2320/4220/4320 BTG Bit Toggle f BOV Branch if Overflow Syntax: [ label ] BTG f,b[,a] Syntax: [ label ] BOV Operands: 0 ≤ f ≤ 255 0≤b<7 a ∈ [0,1] Operands: -128 ≤ n ≤ 127 Operation: if Overflow bit is ‘1’, (PC) + 2 + 2n → PC Status Affected: None Operation: (f) → f Status Affected: None Encoding: Description: bbba ffff 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Read register ‘f’ Process Data Write register ‘f’ Example: BTG PORTC, 4 Before Instruction: PORT
PIC18F2220/2320/4220/4320 BZ Branch if Zero CALL Subroutine Call Syntax: [ label ] BZ Syntax: [ label ] CALL k [,s] Operands: -128 ≤ n ≤ 127 Operands: Operation: if Zero bit is ‘1’, (PC) + 2 + 2n → PC 0 ≤ k ≤ 1048575 s ∈ [0,1] Operation: (PC) + 4 → TOS, k → PC<20:1>; if s = 1, (W) → WS, (STATUS) → STATUSS, (BSR) → BSRS Status Affected: None Status Affected: n None Encoding: 1110 Description: 0000 nnnn nnnn If the Zero bit is ‘1’, then the program will branch.
PIC18F2220/2320/4220/4320 CLRF Clear f Syntax: [ label ] CLRF Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: 000h → f, 1→Z Status Affected: Z Encoding: Description: 0110 f [,a] 101a ffff ffff CLRWDT Clear Watchdog Timer Syntax: [ label ] CLRWDT Operands: None Operation: 000h → WDT, 000h → WDT postscaler, 1 → TO, 1 → PD Status Affected: TO, PD Encoding: 0000 0000 0000 0100 Clears the contents of the specified register.
PIC18F2220/2320/4220/4320 COMF Complement f Syntax: [ label ] COMF Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: ( f ) → dest Status Affected: N, Z Encoding: 0001 Description: 1 Cycles: 1 Q Cycle Activity: Q1 Syntax: [ label ] CPFSEQ Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: (f) – (W), skip if (f) = (W) (unsigned comparison) Status Affected: None Encoding: 0110 001a f [,a] ffff ffff Description: Compares the contents of data memory location ‘f’ to the contents of W by
PIC18F2220/2320/4220/4320 CPFSGT Compare f with W, Skip if f > W CPFSLT Compare f with W, Skip if f < W Syntax: [ label ] CPFSGT Syntax: [ label ] CPFSLT Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: (f) − (W), skip if (f) > (W) (unsigned comparison) Operation: (f) – (W), skip if (f) < (W) (unsigned comparison) Status Affected: None Status Affected: None Encoding: Description: 0110 010a f [,a] ffff ffff Compares the contents of data memory location ‘f’
PIC18F2220/2320/4220/4320 DAW Decimal Adjust W Register DECF Decrement f Syntax: [ label ] DAW Syntax: [ label ] DECF f [,d [,a]] Operands: None Operands: Operation: If [W<3:0> >9] or [DC = 1] then, (W<3:0>) + 6 → W<3:0>; else, (W<3:0>) → W<3:0>; 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) – 1 → dest Status Affected: C, DC, N, OV, Z If [W<7:4> >9] or [C = 1] then, (W<7:4>) + 6 → W<7:4>; else, (W<7:4>) → W<7:4> Status Affected: 0000 Encoding: 0000 0000 0000 Words: 1 Cycles: 1 Q
PIC18F2220/2320/4220/4320 DECFSZ Decrement f, Skip if 0 DCFSNZ Decrement f, Skip if not 0 Syntax: [ label ] DECFSZ f [,d [,a]] Syntax: [ label ] DCFSNZ Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) – 1 → dest, skip if result = 0 Operation: (f) – 1 → dest, skip if result ≠ 0 Status Affected: None Status Affected: None Encoding: 0010 11da ffff ffff Encoding: 0100 11da f [,d [,a]] ffff ffff Description: The contents of registe
PIC18F2220/2320/4220/4320 GOTO Unconditional Branch INCF Increment f Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ k ≤ 1048575 Operands: Operation: k → PC<20:1> Status Affected: None 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) + 1 → dest Status Affected: C, DC, N, OV, Z Encoding: 1st word (k<7:0>) 2nd word(k<19:8>) Description: 1110 1111 GOTO k 1111 k19kkk k7kkk kkkk kkkk0 kkkk8 GOTO allows an unconditional branch anywhere within entire 2 Mbyte memory range.
PIC18F2220/2320/4220/4320 INCFSZ Increment f, Skip if 0 INFSNZ Increment f, Skip if Not 0 Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) + 1 → dest, skip if result = 0 Operation: (f) + 1 → dest, skip if result ≠ 0 Status Affected: None Status Affected: None Encoding: 0011 INCFSZ 11da f [,d [,a]] ffff ffff Encoding: 0100 INFSNZ 10da f [,d [,a]] ffff ffff Description: The contents of regi
PIC18F2220/2320/4220/4320 IORLW Inclusive OR Literal with W IORWF Inclusive OR W with f Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (W) .OR. (f) → dest Status Affected: N, Z IORLW k Operands: 0 ≤ k ≤ 255 Operation: (W) .OR.
PIC18F2220/2320/4220/4320 LFSR Load FSR MOVF Move f Syntax: [ label ] Syntax: [ label ] Operands: 0≤f≤2 0 ≤ k ≤ 4095 Operands: Operation: k → FSRf 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Status Affected: None Operation: f → dest Status Affected: N, Z Encoding: LFSR f,k 1110 1111 1110 0000 00ff k7kkk k11kkk kkkk Description: The 12-bit literal ‘k’ is loaded into the file select register pointed to by ‘f’.
PIC18F2220/2320/4220/4320 MOVFF Move f to f MOVLB Move Literal to Low Nibble in BSR Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ fs ≤ 4095 0 ≤ fd ≤ 4095 Operands: 0 ≤ k ≤ 255 Operation: k → BSR None MOVFF fs,fd Operation: (fs) → fd Status Affected: Status Affected: None Encoding: Encoding: 1st word (source) 2nd word (destin.) 1100 1111 Description: ffff ffff ffff ffff ffffs ffffd The contents of source register ‘fs’ are moved to destination register ‘fd’.
PIC18F2220/2320/4220/4320 MOVLW Move Literal to W MOVWF Move W to f Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ k ≤ 255 Operands: Operation: k→W 0 ≤ f ≤ 255 a ∈ [0,1] Status Affected: None Operation: (W) → f Status Affected: None Encoding: 0000 Description: MOVLW k 1110 kkkk The eight-bit literal ‘k’ is loaded into W.
PIC18F2220/2320/4220/4320 MULLW Multiply Literal with W MULWF Multiply W with f Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: (W) x (f) → PRODH:PRODL Status Affected: None MULLW k Operands: 0 ≤ k ≤ 255 Operation: (W) x k → PRODH:PRODL Status Affected: None Encoding: Description: 0000 1 Cycles: 1 Q Cycle Activity: Q1 Example: kkkk kkkk An unsigned multiplication is carried out between the contents of W and the 8-bit literal ‘k’.
PIC18F2220/2320/4220/4320 NEGF Negate f Syntax: [ label ] Operands: 0 ≤ f ≤ 255 a ∈ [0,1] NEGF Operation: (f)+1→f Status Affected: N, OV, C, DC, Z Encoding: 0110 Description: 1 Cycles: 1 Q Cycle Activity: Q1 Syntax: [ label ] NOP Operands: None Operation: No operation Status Affected: None 0000 1111 ffff Description: 1 Cycles: 1 Decode 0000 xxxx 0000 xxxx No operation.
PIC18F2220/2320/4220/4320 POP Pop Top of Return Stack PUSH Push Top of Return Stack Syntax: [ label ] Syntax: [ label ] Operands: None Operands: None Operation: (TOS) → bit bucket Operation: (PC + 2) → TOS Status Affected: None Status Affected: None Encoding: 0000 POP 0000 0000 0110 Encoding: 0000 PUSH 0000 0000 0101 Description: The TOS value is pulled off the return stack and is discarded. The TOS value then becomes the previous value that was pushed onto the return stack.
PIC18F2220/2320/4220/4320 RCALL Relative Call RESET Reset Syntax: [ label ] RCALL Syntax: [ label ] Operands: Operation: -1024 ≤ n ≤ 1023 Operands: None (PC) + 2 → TOS, (PC) + 2 + 2n → PC Operation: Reset all registers and flags that are affected by a MCLR Reset. Status Affected: None Status Affected: All Encoding: Description: 1101 1nnn nnnn nnnn Subroutine call with a jump up to 1K from the current location. First, return address (PC+2) is pushed onto the stack.
PIC18F2220/2320/4220/4320 RETFIE Return from Interrupt RETLW Return Literal to W Syntax: [ label ] Syntax: [ label ] RETFIE [s] RETLW k Operands: s ∈ [0,1] Operands: 0 ≤ k ≤ 255 Operation: (TOS) → PC, 1 → GIE/GIEH or PEIE/GIEL; if s = 1, (WS) → W, (STATUSS) → STATUS, (BSRS) → BSR, PCLATU, PCLATH are unchanged Operation: k → W, (TOS) → PC, PCLATU, PCLATH are unchanged Status Affected: None Status Affected: 0000 Description: 0000 0001 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 N
PIC18F2220/2320/4220/4320 RETURN Return from Subroutine RLCF Rotate Left f through Carry Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) → dest, (f<7>) → C, (C) → dest<0> Status Affected: C, N, Z RETURN [s] Operands: s ∈ [0,1] Operation: (TOS) → PC; if s = 1, (WS) → W, (STATUSS) → STATUS, (BSRS) → BSR, PCLATU, PCLATH are unchanged Status Affected: None Encoding: 0000 Encoding: 0000 0001 001s Description: Return from subroutine.
PIC18F2220/2320/4220/4320 RLNCF Rotate Left f (no carry) RRCF Rotate Right f through Carry Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) → dest, (f<7>) → dest<0> Operation: Status Affected: N, Z (f) → dest, (f<0>) → C, (C) → dest<7> Status Affected: C, N, Z Encoding: 0100 Description: RLNCF 01da f [,d [,a]] ffff ffff The contents of register ‘f’ are rotated one bit to the
PIC18F2220/2320/4220/4320 RRNCF Rotate Right f (no carry) SETF Set f Syntax: [ label ] Syntax: [ label ] SETF Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operands: 0 ≤ f ≤ 255 a ∈ [0,1] (f) → dest, (f<0>) → dest<7> Operation: FFh → f Operation: Status Affected: None Status Affected: N, Z Encoding: 0100 Description: RRNCF 00da f [,d [,a]] Encoding: ffff ffff The contents of register ‘f’ are rotated one bit to the right. If ‘d’ is ‘0’, the result is placed in W.
PIC18F2220/2320/4220/4320 SLEEP Enter Sleep mode SUBFWB Subtract f from W with Borrow Syntax: [ label ] SLEEP Syntax: [ label ] SUBFWB Operands: None Operands: Operation: 00h → WDT, 0 → WDT postscaler, 1 → TO, 0 → PD 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (W) – (f) – (C) → dest Status Affected: N, OV, C, DC, Z Status Affected: TO, PD Encoding: 0000 Encoding: 0000 0000 0011 Description: The Power-Down status bit (PD) is cleared. The Time-out status bit (TO) is set.
PIC18F2220/2320/4220/4320 SUBLW Subtract W from Literal SUBWF Subtract W from f Syntax: [ label ] SUBLW k Syntax: [ label ] SUBWF Operands: 0 ≤ k ≤ 255 Operands: Operation: k – (W) → W Status Affected: N, OV, C, DC, Z 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) – (W) → dest Status Affected: N, OV, C, DC, Z Encoding: 0000 1000 kkkk kkkk Description: W is subtracted from the eight-bit literal ‘k’. The result is placed in W.
PIC18F2220/2320/4220/4320 SUBWFB Subtract W from f with Borrow Syntax: [ label ] SUBWFB Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) – (W) – (C) → dest Status Affected: N, OV, C, DC, Z Encoding: Description: 0101 1 Cycles: 1 Q Cycle Activity: Q1 10da ffff ffff REG, 1, 0 Before Instruction REG W C = = = REG W C Z N = = = = = Example 2: 0x19 0x0D 0x01 (0001 1001) (0000 1101) 0x0C 0x0D 0x01 0x00 0x00 (0000 1011) (0000 1101) ; result is positive SUBWFB REG, 0, 0 Before
PIC18F2220/2320/4220/4320 SWAPF Swap f Syntax: [ label ] SWAPF f [,d [,a]] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f<3:0>) → dest<7:4>, (f<7:4>) → dest<3:0> Status Affected: None Encoding: 0011 Description: ffff ffff The upper and lower nibbles of register ‘f’ are exchanged. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value.
PIC18F2220/2320/4220/4320 TBLRD Table Read TBLRD Table Read (cont’d) Syntax: [ label ] Example1: TBLRD Operands: None Operation: if TBLRD *, (Prog Mem (TBLPTR)) → TABLAT, TBLPTR - No Change; if TBLRD *+, (Prog Mem (TBLPTR)) → TABLAT, (TBLPTR) +1 → TBLPTR; if TBLRD *-, (Prog Mem (TBLPTR)) → TABLAT, (TBLPTR) -1 → TBLPTR; if TBLRD +*, (TBLPTR) +1 → TBLPTR, (Prog Mem (TBLPTR)) → TABLAT TBLRD ( *; *+; *-; +*) Before Instruction Status Affected:None Encoding: 0000 0000 0000 10nn nn=0 * =1 *+ =2
PIC18F2220/2320/4220/4320 TBLWT Table Write TBLWT Table Write (Continued) Syntax: [ label ] Words: 1 TBLWT ( *; *+; *-; +*) Operands: None Cycles: 2 Operation: if TBLWT*, (TABLAT) → Holding Register, TBLPTR - No Change; if TBLWT*+, (TABLAT) → Holding Register, (TBLPTR) +1 → TBLPTR; if TBLWT*-, (TABLAT) → Holding Register, (TBLPTR) -1 → TBLPTR; if TBLWT+*, (TBLPTR) +1 → TBLPTR, (TABLAT) → Holding Register Q Cycle Activity: Status Affected: None Encoding: Description: 0000 0000 0000 11nn nn=
PIC18F2220/2320/4220/4320 TSTFSZ Test f, Skip if 0 XORLW Exclusive OR Literal with W Syntax: [ label ] TSTFSZ f [,a] Syntax: [ label ] XORLW k Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operands: 0 ≤ k ≤ 255 Operation: skip if f = 0 Operation: (W) .XOR.
PIC18F2220/2320/4220/4320 XORWF Exclusive OR W with f Syntax: [ label ] XORWF Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (W) .XOR. (f) → dest Status Affected: N, Z Encoding: 0001 10da f [,d [,a]] ffff ffff Description: Exclusive OR the contents of W with register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in the register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value.
PIC18F2220/2320/4220/4320 NOTES: DS39599G-page 300 © 2007 Microchip Technology Inc.
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PIC18F2220/2320/4220/4320 25.2 MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging.
PIC18F2220/2320/4220/4320 25.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator The MPLAB ICE 2000 In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PIC microcontrollers. Software control of the MPLAB ICE 2000 In-Circuit Emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment.
PIC18F2220/2320/4220/4320 25.11 PICSTART Plus Development Programmer 25.13 Demonstration, Development and Evaluation Boards The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PIC devices in DIP packages up to 40 pins.
PIC18F2220/2320/4220/4320 26.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (†) Ambient temperature under bias.............................................................................................................-55°C to +125°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD, MCLR and RA4) .......................................
PIC18F2220/2320/4220/4320 FIGURE 26-1: PIC18F2220/2320/4220/4320 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V Voltage 5.0V PIC18F2X20/4X20 4.5V 4.2V 4.0V 3.5V 3.0V 2.5V 2.0V 40 MHz Frequency FIGURE 26-2: PIC18F2220/2320/4220/4320 VOLTAGE-FREQUENCY GRAPH (EXTENDED) 6.0V 5.5V Voltage 5.0V PIC18F2X20/4X20 4.5V 4.2V 4.0V 3.5V 3.0V 2.5V 2.0V 25 MHz Frequency DS39599G-page 306 © 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320 FIGURE 26-3: PIC18LF2220/2320/4220/4320 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V Voltage 5.0V PIC18LF2X20/4X20 4.5V 4.2V 4.0V 3.5V 3.0V 2.5V 2.0V 40 MHz 4 MHz Frequency FMAX = (16.36 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz Note: VDDAPPMIN is the minimum voltage of the PIC® device in the application. © 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320 26.1 DC Characteristics: Supply Voltage PIC18F2220/2320/4220/4320 (Industrial) PIC18LF2220/2320/4220/4320 (Industrial) PIC18LF2220/2320/4220/4320 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18F2220/2320/4220/4320 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No.
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PIC18F2220/2320/4220/4320 26.3 DC Characteristics: PIC18F2220/2320/4220/4320 (Industrial) PIC18LF2220/2320/4220/4320 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended DC CHARACTERISTICS Param Symbol No. VIL Characteristic Min Max Units Conditions with TTL Buffer VSS 0.15 VDD V VDD < 4.5V — 0.8 V 4.5V ≤ VDD ≤ 5.5V with Schmitt Trigger Buffer RC3 and RC4 VSS VSS 0.2 VDD 0.
PIC18F2220/2320/4220/4320 26.3 DC Characteristics: PIC18F2220/2320/4220/4320 (Industrial) PIC18LF2220/2320/4220/4320 (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended DC CHARACTERISTICS Param Symbol No. VOL D080 Characteristic D080A OSC2/CLKO (RC mode) D083A VOH D090 D090A OSC2/CLKO (RC mode) D092A D150 VOD Units Conditions — 0.6 V IOL = 8.5 mA, VDD = 4.
PIC18F2220/2320/4220/4320 TABLE 26-1: MEMORY PROGRAMMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended DC Characteristics Param No. Sym Characteristic Min Typ† Max Units V Conditions Internal Program Memory Programming Specifications VPP Voltage on MCLR/VPP pin 9.00 — 13.25 D112 IPP Current into MCLR/VPP pin — — 300 μA D113 IDDP Supply Current during Programming — — 1.
PIC18F2220/2320/4220/4320 TABLE 26-2: COMPARATOR SPECIFICATIONS Operating Conditions: 3.0V < VDD < 5.5V, -40°C < TA < +125°C, unless otherwise stated. Param No. Sym Characteristics Min Typ Max Units D300 VIOFF Input Offset Voltage — ±5.0 ±10 mV D301 VICM Input Common Mode Voltage* 0 — VDD – 1.
PIC18F2220/2320/4220/4320 TABLE 26-4: LOW-VOLTAGE DETECT CHARACTERISTICS PIC18LF2220/2320/4220/4320 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18F2220/2320/4220/4320 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No.
PIC18F2220/2320/4220/4320 TABLE 26-4: LOW-VOLTAGE DETECT CHARACTERISTICS (CONTINUED) PIC18LF2220/2320/4220/4320 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18F2220/2320/4220/4320 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No.
PIC18F2220/2320/4220/4320 TABLE 26-4: LOW-VOLTAGE DETECT CHARACTERISTICS (CONTINUED) PIC18LF2220/2320/4220/4320 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18F2220/2320/4220/4320 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No.
PIC18F2220/2320/4220/4320 26.4 26.4.1 AC (Timing) Characteristics TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2.
PIC18F2220/2320/4220/4320 26.4.2 TIMING CONDITIONS Note: The temperature and voltages specified in Table 26-5 apply to all timing specifications unless otherwise noted. Figure 26-5 specifies the load conditions for the timing specifications.
PIC18F2220/2320/4220/4320 26.4.3 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 26-6: EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL) Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 4 3 4 2 CLKO TABLE 26-6: Param. No. 1A EXTERNAL CLOCK TIMING REQUIREMENTS Symbol FOSC Characteristic Min Max External CLKI Frequency(1) DC 40 MHz EC, ECIO (industrial) DC 25 MHz EC, ECIO (extended) DC 4 MHz RC osc 0.1 1 MHz XT osc 4 25 MHz HS osc 4 10 MHz HS + PLL osc (industrial) 4 6.
PIC18F2220/2320/4220/4320 TABLE 26-7: Param No. PLL CLOCK TIMING SPECIFICATIONS (VDD = 4.2V TO 5.5V) Sym Characteristic Min Typ† Max Units Conditions F10 FOSC Oscillator Frequency Range 4 — 10 MHz HS mode only F11 FSYS On-Chip VCO System Frequency 16 — 40 MHz HS mode only F12 tPLL PLL Start-up Time (Lock Time) — — 2 ms ΔCLK CLKO Stability (Jitter) -2 — +2 % F13 † Data in “Typ” column is at 5V, 25°C unless otherwise stated.
PIC18F2220/2320/4220/4320 FIGURE 26-7: CLKO AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 CLKO 13 14 19 12 18 16 I/O pin (Input) 15 17 I/O pin (Output) Note: 20, 21 Refer to Figure 26-5 for load conditions. TABLE 26-9: Param No.
PIC18F2220/2320/4220/4320 FIGURE 26-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal Reset Watchdog Timer Reset 31 34 34 I/O pins Note: Refer to Figure 26-5 for load conditions. FIGURE 26-9: BROWN-OUT RESET TIMING VDD BVDD 35 VBGAP = 1.2V VIRVST Enable Internal Reference Voltage Internal Reference Voltage Stable © 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320 TABLE 26-10: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET REQUIREMENTS Param. Symbol No.
PIC18F2220/2320/4220/4320 TABLE 26-11: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param Symbol No. Characteristic 40 TT0H T0CKI High Pulse Width 41 TT0L T0CKI Low Pulse Width 42 TT0P T0CKI Period No prescaler Min Max Units 0.5 TCY + 20 — ns With prescaler No prescaler 10 — ns 0.
PIC18F2220/2320/4220/4320 TABLE 26-12: CAPTURE/COMPARE/PWM REQUIREMENTS (ALL CCP MODULES) Param Symbol No. 50 51 TCCL Characteristic CCPx Input Low Time TCCH Max Units 0.5 TCY + 20 — ns PIC18FXX20 10 — ns PIC18LFXX20 20 — ns 0.
PIC18F2220/2320/4220/4320 TABLE 26-13: PARALLEL SLAVE PORT REQUIREMENTS (PIC18F4X20) Param. No.
PIC18F2220/2320/4220/4320 TABLE 26-14: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0) Param No. Symbol Characteristic Min Max Units 70 TSSL2SCH, TSSL2SCL SS ↓ to SCK ↓ or SCK ↑ Input 71 TSCH SCK Input High Time (Slave mode) Continuous 1.25 TCY + 30 — ns Single Byte 40 — ns SCK Input Low Time (Slave mode) Continuous 1.25 TCY + 30 — ns Single Byte 40 — ns 100 — ns 1.
PIC18F2220/2320/4220/4320 TABLE 26-15: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1) Param. No. 71 Symbol Characteristic Min TSCH SCK Input High Time (Slave mode) TSCL SCK Input Low Time (Slave mode) 73 TDIV2SCH, TDIV2SCL Setup Time of SDI Data Input to SCK Edge 73A TB2B Last Clock Edge of Byte 1 to the 1st Clock Edge of Byte 2 74 TSCH2DIL, TSCL2DIL Hold Time of SDI Data Input to SCK Edge 75 TDOR SDO Data Output Rise Time 71A 72 72A Continuous Max Units 1.
PIC18F2220/2320/4220/4320 TABLE 26-16: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0) Param No. Symbol Characteristic 70 TSSL2SCH, SS ↓ to SCK ↓ or SCK ↑ Input TSSL2SCL 71 TSCH SCK Input High Time (Slave mode) 71A TSCL 72 SCK Input Low Time (Slave mode) 72A Min Max Units Conditions TCY — ns Continuous 1.25 TCY + 30 — ns Single Byte 40 — ns Continuous 1.
PIC18F2220/2320/4220/4320 TABLE 26-17: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1) Param No. Symbol Characteristic 70 TSSL2SCH, SS ↓ to SCK ↓ or SCK ↑ Input TSSL2SCL 71 TSCH 71A TSCL 72 72A Min Max Units Conditions TCY — ns SCK Input High Time (Slave mode) Continuous 1.25 TCY + 30 — ns Single Byte 40 — ns SCK Input Low Time (Slave mode) Continuous 1.
PIC18F2220/2320/4220/4320 TABLE 26-18: I2C™ BUS START/STOP BITS REQUIREMENTS (SLAVE MODE) Param. Symbol No.
PIC18F2220/2320/4220/4320 TABLE 26-19: I2C™ BUS DATA REQUIREMENTS (SLAVE MODE) Param. Symbol No. 100 101 102 THIGH TLOW TR Characteristic Clock High Time Clock Low Time Min Max Units Conditions 100 kHz mode 4.0 — μs PIC18FXX20 must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — μs PIC18FXX20 must operate at a minimum of 10 MHz MSSP module 1.5 TCY — 100 kHz mode 4.7 — μs PIC18FXX20 must operate at a minimum of 1.5 MHz 400 kHz mode 1.
PIC18F2220/2320/4220/4320 FIGURE 26-19: MASTER SSP I2C™ BUS START/STOP BITS TIMING WAVEFORMS SCL 93 91 90 92 SDA Stop Condition Start Condition Note: Refer to Figure 26-5 for load conditions. TABLE 26-20: MASTER SSP I2C™ BUS START/STOP BITS REQUIREMENTS Param. Symbol No.
PIC18F2220/2320/4220/4320 TABLE 26-21: MASTER SSP I2C™ BUS DATA REQUIREMENTS Param. Symbol No.
PIC18F2220/2320/4220/4320 FIGURE 26-21: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RC6/TX/CK pin 121 121 RC7/RX/DT pin 120 Note: 122 Refer to Figure 26-5 for load conditions. TABLE 26-22: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param No.
PIC18F2220/2320/4220/4320 TABLE 26-24: A/D CONVERTER CHARACTERISTICS: PIC18F2220/2320/4220/4320 (INDUSTRIAL) PIC18F2220/2320/4220/4320 (EXTENDED) PIC18LF2220/2320/4220/4320 (INDUSTRIAL) Param Symbol No. Characteristic Min Typ Max Units ΔVREF ≥ 3.0V A01 NR Resolution — — 10 A03 EIL Integral Linearity Error — — <±1 LSb ΔVREF ≥ 3.0V A04 EDL Differential Linearity Error — — <±1 LSb ΔVREF ≥ 3.0V A06 EOFF Offset Error — — <±1 LSb ΔVREF ≥ 3.
PIC18F2220/2320/4220/4320 FIGURE 26-23: A/D CONVERSION TIMING BSF ADCON0, GO (Note 2) 131 Q4 A/D CLK 130 132 9 A/D DATA 8 7 ... ... 2 1 0 NEW_DATA OLD_DATA ADRES TCY ADIF GO DONE SAMPLING STOPPED SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
PIC18F2220/2320/4220/4320 27.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
PIC18F2220/2320/4220/4320 FIGURE 27-3: MAXIMUM IDD vs. FOSC OVER VDD PRI_RUN, EC MODE, -40°C TO +125°C 0.7 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 0.6 5.5V 5.0V 0.5 4.5V IDD (mA) 0.4 4.0V 0.3 3.5V 3.0V 0.2 2.5V 0.1 2.0V 0.0 0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 FOSC (MHz) TYPICAL IDD vs. FOSC OVER VDD PRI_RUN, EC MODE, +25°C FIGURE 27-4: 2.
PIC18F2220/2320/4220/4320 FIGURE 27-5: MAXIMUM IDD vs. FOSC OVER VDD PRI_RUN, EC MODE, -40°C TO +125°C 2.5 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 2.0 5.5V 5.0V 1.5 IDD (mA) 4.5V 4.0V 1.0 3.5V 3.0V 2.5V 0.5 2.0V 0.0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 FOSC (MHz) TYPICAL IDD vs.
PIC18F2220/2320/4220/4320 FIGURE 27-7: MAXIMUM IDD vs. FOSC OVER VDD PRI_RUN, EC MODE, -40°C TO +125°C 16 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 14 5.5V 5.0V 12 4.0V 10 IDD (mA) 4.5V 8 3.5V 6 4 3.0V 2 2.5V 2.0V 0 4 8 12 16 20 24 28 32 36 40 FOSC (MHz) FIGURE 27-8: TYPICAL IDD vs. FOSC OVER VDD PRI_IDLE, EC MODE, +25°C 0.
PIC18F2220/2320/4220/4320 FIGURE 27-9: MAXIMUM IDD vs. FOSC OVER VDD PRI_IDLE, EC MODE, -40°C TO +85°C 0.045 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 0.040 5.5V 0.035 5.0V 0.030 IDD (mA) 4.5V 0.025 4.0V 0.020 3.5V 3.0V 0.015 2.5V 0.010 2.0V 0.005 0.000 0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 FOSC (MHz) FIGURE 27-10: MAXIMUM IDD vs. FOSC OVER VDD PRI_IDLE, EC MODE, -40°C TO +125°C 0.100 0.
PIC18F2220/2320/4220/4320 FIGURE 27-11: TYPICALyp IDD vs. FOSC OVER VDD PRI_IDLE, EC MODE, +25°C _ 600 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 500 5.5V 5.0V 400 IDD (μA) 4.5V 4.0V 300 3.5V 3.0V 200 2.5V 2.0V 100 0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 FOSC (MHz) FIGURE 27-12: MAXIMUM IDD vs.
PIC18F2220/2320/4220/4320 FIGURE 27-13: TYPICAL IDD vs. FOSC OVER VDD PRI_IDLE, EC MODE, +25°C 6.0 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 5.5 5.0 4.5 5.5V 5.0V 4.0 IDD (mA) 3.5 4.5V 3.0 2.5 4.0V 2.0 3.5V 1.5 1.0 3.0V 0.5 2.5V 2.0V 0.0 4 8 12 16 20 24 28 32 36 40 FOSC (MHz) FIGURE 27-14: MAXIMUM IDD vs. FOSC OVER VDD PRI_IDLE, EC MODE, -40°C TO +125°C 6.0 5.5 5.
PIC18F2220/2320/4220/4320 FIGURE 27-15: TYPICAL IPD vs. VDD (+25°C), 125 kHz TO 8 MHz RC_RUN MODE, ALL PERIPHERALS DISABLED 3000 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 8 MHz 2500 250 kHz and 500 kHz curves are bounded by 125 kHz and 1 MHz IPD (μA) 2000 1500 4 MHz 1000 2 MHz 500 1 MHz 125 kHz 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 27-16: MAXIMUM IPD vs.
PIC18F2220/2320/4220/4320 FIGURE 27-17: TYPICAL AND MAXIMUM IPD vs. VDD (-40°C TO +125°C), 31.25 kHz RC_RUN, ALL PERIPHERALS DISABLED 100 Max (+125°C) Max (+85°C) IPD (μA) Typ (+25°C) 10 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 1 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 27-18: TYPICAL IPD vs.
PIC18F2220/2320/4220/4320 FIGURE 27-19: MAXIMUM IPD vs. VDD (-40°C TO +125°C), 125 kHz TO 8 MHz RC_IDLE, ALL PERIPHERALS DISABLED 800 8 MHz 750 250 kHz and 500 kHz curves are bounded by 125 kHz and 1 MHz 700 4 MHz 650 2 MHz 1 MHz 125 kHz 600 550 IPD (μA) 500 450 400 350 300 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 250 200 150 100 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 27-20: TYPICAL AND MAXIMUM IPD vs.
PIC18F2220/2320/4220/4320 FIGURE 27-21: IPD SEC_RUN MODE, -10°C TO +70°C 32.768 kHz XTAL 2 X 22 pF, ALL PERIPHERALS DISABLED 80 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 70 60 Max (+70°C) IPD (μA) 50 40 Typ (+25°C) 30 20 10 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 5.0 5.5 VDD (V) FIGURE 27-22: IPD SEC_IDLE, -10°C TO +70°C 32.
PIC18F2220/2320/4220/4320 FIGURE 27-23: TOTAL IPD, -40°C TO +125°C SLEEP MODE, ALL PERIPHERALS DISABLED 100 Max (+125°C) 10 Max (+85°C) IPD (μA) 1 0.1 Typ (+25°C) 0.01 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 0.001 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 27-24: VOH vs. IOH OVER TEMPERATURE (-40°C TO +125°C), VDD = 3.0V 3.0 2.5 2.0 VOH (V) Max (+125°C) 1.5 Typ (+25°C) Min (+125°C) 1.0 0.5 0.
PIC18F2220/2320/4220/4320 FIGURE 27-25: VOH vs. IOH OVER TEMPERATURE (-40°C TO +125°C), VDD = 5.0V 5.0 4.5 Max (+125°C) 4.0 Typ (+25°C) 3.5 VOH (V) 3.0 2.5 Min (+125°C) 2.0 1.5 1.0 0.5 0.0 0 5 10 15 20 25 IOH (-mA) FIGURE 27-26: (-40°C TO +125°C), VDD = 3.0V VOL vs. IOL OVER TEMPERATURE ( ) 3.0 Max (+125°C) 2.5 Max (+85°C) VOL (V) 2.0 1.5 Typ (+25°C) 1.0 0.5 Min (+125°C) 0.0 0 5 10 15 20 25 IOL (-mA) © 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320 FIGURE 27-27: VOL vs. IOL OVER TEMPERATURE (-40°C TO +125°C), VDD = 5.0V 1.0 0.9 Max (+125°C) 0.8 0.7 0.6 VOL (V) Max (+85°C) 0.5 0.4 Typ (+25°C) 0.3 0.2 Min (+125°C) 0.1 0.0 0 5 10 15 20 25 IOL (-mA) FIGURE 27-28: Δ IPD TIMER1 OSCILLATOR, -10°C TO +70°C SLEEP MODE, TMR1 COUNTER DISABLED 5.0 4.5 Max (-10°C to +70°C) 4.0 3.5 IPD (μA) 3.0 Typ (+25°C) 2.5 2.0 1.
PIC18F2220/2320/4220/4320 FIGURE 27-29: ΔIPD FSCM vs. VDD OVER TEMPERATURE PRI_IDLE, EC OSCILLATOR AT 32 kHz, -40°C TO +125°C 4.5 4.0 Max (-40°C) 3.5 ΔIPD (μA) 3.0 2.5 Typ (+25°C) 2.0 1.5 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 1.0 0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PIC18F2220/2320/4220/4320 FIGURE 27-31: ΔIPD LVD vs. VDD SLEEP MODE, LVD = 2.00V-2.12V 50 45 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 40 Max (+125°C) 35 Max (+85°C) IPD (μA) 30 Typ (+25°C) 25 20 15 10 Low-Voltage Detection Range 5 Normal Operating Range 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 5.0 5.5 VDD (V) FIGURE 27-32: ΔIPD BOR vs. VDD, -40°C TO +125°C SLEEP MODE, BOR ENABLED AT 2.00V-2.
PIC18F2220/2320/4220/4320 FIGURE 27-33: ΔIPD A/D, -40°C TO +125°C SLEEP MODE, A/D ENABLED (NOT CONVERTING) 10 Max (+125°C) 1 IPD (μA) Max (+85°C) 0.1 0.01 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) Typ (+25°C) 0.001 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 27-34: AVERAGE FOSC vs. VDD FOR VARIOUS R’S EXTERNAL RC MODE, C = 20 pF, TEMPERATURE = +25°C 5.0 Operation above 4 MHz is not recomended 4.5 4.0 5.1K 3.
PIC18F2220/2320/4220/4320 FIGURE 27-35: AVERAGE FOSC vs. VDD FOR VARIOUS R’S EXTERNAL RC MODE, C = 100 pF, TEMPERATURE = +25°C 2.0 1.8 1.6 5.1K 1.4 Freq (MHz) 1.2 1.0 10K 0.8 0.6 0.4 33K 0.2 100K 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 27-36: AVERAGE FOSC vs. VDD FOR VARIOUS R’S EXTERNAL RC MODE, C = 300 pF, TEMPERATURE = +25°C 0.8 0.7 0.6 Freq (MHz) 0.5 5.1K 0.4 0.3 10K 0.2 0.1 33K 100K 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PIC18F2220/2320/4220/4320 28.0 PACKAGING INFORMATION 28.1 Package Marking Information 28-Lead SPDIP Example PIC18F2220-I/SP e3 0710017 XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 28-Lead SOIC Example XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN 40-Lead PDIP Example XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX YYWWNNN Legend: XX...
PIC18F2220/2320/4220/4320 Package Marking Information (Continued) 44-Lead TQFP XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 44-Lead QFN XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN DS39599G-page 366 Example PIC18F4320 -I/PT e3 0710017 Example PIC18F4220 -I/ML e3 0710017 © 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320 28.2 Package Details The following sections give the technical details of the packages.
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PIC18F2220/2320/4220/4320 /HDG 3ODVWLF 7KLQ 4XDG )ODWSDFN 37 ± [ [ PP %RG\ PP >74)3@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ © 2007 Microchip Technology Inc.
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PIC18F2220/2320/4220/4320 /HDG 3ODVWLF 4XDG )ODW 1R /HDG 3DFNDJH 0/ ± [ PP %RG\ >4)1@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ © 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320 NOTES: DS39599G-page 374 © 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320 APPENDIX A: REVISION HISTORY Revision A (June 2002) Original data sheet for PIC18F2X20/4X20 devices. Revision B (October 2002) This revision includes major changes to Section 2.0 “Oscillator Configurations” and Section 3.0 “Power-Managed Modes”, updates to the Electrical Specifications in Section 26.0 “Electrical Characteristics” and minor corrections to the data sheet text. Revision C (October 2003) This revision includes updates to the Electrical Specifications in Section 26.
PIC18F2220/2320/4220/4320 APPENDIX B: DEVICE DIFFERENCES The differences between the devices listed in this data sheet are shown in Table B-1.
PIC18F2220/2320/4220/4320 APPENDIX C: CONVERSION CONSIDERATIONS This appendix discusses the considerations for converting from previous versions of a device to the ones listed in this data sheet. Typically, these changes are due to the differences in the process technology used. An example of this type of conversion is from a PIC16C74A to a PIC16C74B. Not Applicable © 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320 APPENDIX E: MIGRATION FROM MID-RANGE TO ENHANCED DEVICES A detailed discussion of the differences between the mid-range MCU devices (i.e., PIC16CXXX) and the enhanced devices (i.e., PIC18FXXX) is provided in AN716, “Migrating Designs from PIC16C74A/74B to PIC18C442.” The changes discussed, while device specific, are generally applicable to all mid-range to enhanced device migrations.
PIC18F2220/2320/4220/4320 INDEX A A/D ................................................................................... 211 A/D Converter Interrupt, Configuring ....................... 215 Acquisition Requirements ........................................ 216 ADCON0 Register .................................................... 211 ADCON1 Register .................................................... 211 ADCON2 Register .................................................... 211 ADRESH Register ................
PIC18F2220/2320/4220/4320 C C Compilers MPLAB C18 ............................................................. 302 MPLAB C30 ............................................................. 302 CALL ................................................................................ 272 Capture (CCP Module) ..................................................... 135 Associated Registers ............................................... 137 CCP Pin Configuration .............................................
PIC18F2220/2320/4220/4320 E I ECCP ............................................................................... 141 Auto-Shutdown ........................................................ 149 And Automatic Restart ..................................... 151 Capture and Compare Modes .................................. 142 Outputs .................................................................... 142 Standard PWM Mode ............................................... 142 Start-up Considerations ............
PIC18F2220/2320/4220/4320 BTFSC ..................................................................... 270 BTFSS ...................................................................... 270 BTG .......................................................................... 271 BZ ............................................................................. 272 CALL ........................................................................ 272 CLRF ......................................................................
PIC18F2220/2320/4220/4320 MPLINK Object Linker/MPLIB Object Librarian ............... 302 MSSP ............................................................................... 155 Control Registers (General) ..................................... 155 Enabling SPI I/O ...................................................... 159 I2C Master Mode ...................................................... 179 I2C Mode I2C Mode. See I2C I2C Slave Mode ........................................................
PIC18F2220/2320/4220/4320 PORTD Associated Registers ............................................... 110 LATD Register .......................................................... 109 Parallel Slave Port (PSP) Function .......................... 109 PORTD Register ...................................................... 109 TRISD Register ........................................................ 109 PORTE Analog Port Pins ...................................................... 113 Associated Registers ...........
PIC18F2220/2320/4220/4320 OSCTUN2 (INTRC Oscillator Tuning) ........................ 24 PIE1 (Peripheral Interrupt Enable 1) .......................... 94 PIE2 (Peripheral Interrupt Enable 2) .......................... 95 PIR1 (Peripheral Interrupt Request (Flag) 1) ............................................................. 92 PIR2 (Peripheral Interrupt Request (Flag) 2) ............................................................. 93 PWM1CON (PWM Configuration) ............................
PIC18F2220/2320/4220/4320 Timer2 .............................................................................. 127 Associated Registers ............................................... 128 MSSP Clock Shift ............................................. 127, 128 Operation ................................................................. 127 Postscaler. See Postscaler, Timer2. PR2 Register .................................................... 127, 138 Prescaler. See Prescaler, Timer2. TMR2 Register ............
PIC18F2220/2320/4220/4320 Timing Diagrams and Specifications ................................ 328 A/D Conversion Requirements ................................ 346 Capture/Compare/PWM Requirements ................... 334 CLKO and I/O Requirements ................................... 330 DC Characteristics - Internal RC Accuracy .............. 329 Example SPI Mode Requirements (Master Mode, CKE = 0) .................................. 336 Example SPI Mode Requirements (Master Mode, CKE = 1) ....................
PIC18F2220/2320/4220/4320 NOTES: DS39599G-page 388 © 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
PIC18F2220/2320/4220/4320 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
PIC18F2220/2320/4220/4320 PIC18F2220/2320/4220/4320 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. − PART NO. Device Device X Temperature Range /XX XXX Package Pattern PIC18F2220/2320/4220/4320(1), PIC18F2220/2320/4220/4320T(1,2); VDD range 4.2V to 5.5V Examples: a) b) c) PIC18LF4320-I/P 301 = Industrial temp., PDIP package, Extended VDD limits, QTP pattern #301. PIC18LF2220-I/SO = Industrial temp.
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