Datasheet

 2010 Microchip Technology Inc. Preliminary DS41350E-page 91
PIC18F/LF1XK50
REGISTER 9-8: WPUB: WEAK PULL-UP PORTB REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 U-0 U-0 U-0 U-0
WPUB7 WPUB6 WPUB5 WPUB4
— — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-4 WPUB<7:4>: Weak Pull-up Enable bit
1 = Pull-up enabled
0 = Pull-up disabled
bit 3-0 Unimplemented: Read as ‘0’
REGISTER 9-9: IOCB: INTERRUPT-ON-CHANGE PORTB REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0
IOCB7 IOCB6 IOCB5 IOCB4 — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-4 IOCB<7:4>: Interrupt-on-change bits
1 = Interrupt-on-change enabled
0 = Interrupt-on-change disabled
bit 3-0 Unimplemented: Read as ‘0’
REGISTER 9-10: LATB: PORTB DATA LATCH REGISTER
R/W-x R/W-x R/W-x R/W-x U-0 U-0 U-0 U-0
LATB7 LATB6 LATB5 LATB4
— — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-4 LATB<7:4>: RB<7:4> Port I/O Output Latch Register bits
bit 3-0 Unimplemented: Read as ‘0’