Datasheet
2010 Microchip Technology Inc. Preliminary DS41350E-page 41
PIC18F1XK50/PIC18LF1XK50
TABLE 3-2: REGISTER FILE SUMMARY (PIC18F/LF1XK50)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Details
on
page:
TOSU
— — — Top-of-Stack Upper Byte (TOS<20:16>) ---0 0000 285, 30
TOSH Top-of-Stack, High Byte (TOS<15:8>) 0000 0000 285, 30
TOSL Top-of-Stack, Low Byte (TOS<7:0>) 0000 0000 285, 30
STKPTR STKFUL STKUNF
— SP4 SP3 SP2 SP1 SP0 00-0 0000 285, 31
PCLATU
— — — Holding Register for PC<20:16> ---0 0000 285, 30
PCLATH Holding Register for PC<15:8> 0000 0000 285, 30
PCL PC, Low Byte (PC<7:0>) 0000 0000 285, 30
TBLPTRU
— — — Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) ---0 0000 285, 54
TBLPTRH Program Memory Table Pointer, High Byte (TBLPTR<15:8>) 0000 0000 285, 54
TBLPTRL Program Memory Table Pointer, Low Byte (TBLPTR<7:0>) 0000 0000 285, 54
TABLAT Program Memory Table Latch 0000 0000 285, 54
PRODH Product Register, High Byte xxxx xxxx 285, 65
PRODL Product Register, Low Byte xxxx xxxx 285, 65
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF 0000 000x 285, 70
INTCON2 RABPU
INTEDG0 INTEDG1 INTEDG2 —TMR0IP— RABIP 1111 -1-1 285, 71
INTCON3 INT2IP INT1IP
— INT2IE INT1IE — INT2IF INT1IF 11-0 0-00 285, 72
INDF0 Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register) N/A 285, 47
POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register) N/A 285, 47
POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register) N/A 285, 47
PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) N/A 285, 47
PLUSW0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) – value
of FSR0 offset by W
N/A 285, 47
FSR0H
— — — — Indirect Data Memory Address Pointer 0, High Byte ---- 0000 285, 47
FSR0L Indirect Data Memory Address Pointer 0, Low Byte xxxx xxxx 285, 47
WREG Working Register xxxx xxxx 285
INDF1 Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register) N/A 285, 47
POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register) N/A 285, 47
POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register) N/A 285, 47
PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) N/A 285, 47
PLUSW1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) – value
of FSR1 offset by W
N/A 285, 47
FSR1H
— — — — Indirect Data Memory Address Pointer 1, High Byte ---- 0000 286, 47
FSR1L Indirect Data Memory Address Pointer 1, Low Byte xxxx xxxx 286, 47
BSR
— — — — Bank Select Register ---- 0000 286, 35
INDF2 Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register) N/A 286, 47
POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register) N/A 286, 47
POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register) N/A 286, 47
PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) N/A 286, 47
PLUSW2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) – value
of FSR2 offset by W
N/A 286, 47
FSR2H
— — — — Indirect Data Memory Address Pointer 2, High Byte ---- 0000 286, 47
FSR2L Indirect Data Memory Address Pointer 2, Low Byte xxxx xxxx 286, 47
STATUS
— — —NOV Z DCC---x xxxx 286, 45
Legend: x = unknown, u = unchanged, — = unimplemented, q = value depends on condition
Note 1: The SBOREN bit is only available when the BOREN<1:0> Configuration bits = 01; otherwise it is disabled and reads as ‘0’. See
Section 23.4 “Brown-out Reset (BOR)”.
2: The RA3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0). Otherwise, RA3 reads as ‘0’. This bit is
read-only.
3: Bits RA0 and RA1 are available only when USB is disabled.