Datasheet

 2010 Microchip Technology Inc. Preliminary DS41350E-page 289
PIC18F/LF1XK50
USTAT
F63h
-xxx xxx- -xxx xxx- -uuu uuu-
UIR
F62h
-000 0000 -000 0000 -uuu uuuu
UCFG
F61h
0--0 -000 0--0 -000 u--u -uuu
UIE
F60h
-000 0000 -000 0000 -uuu uuuu
UEIR
F5Fh
0--0 0000 0--0 0000 u--u uuuu
UFRMH
F5Eh
---- -xxx ---- -xxx ---- -uuu
UFRML
F5Dh
xxxx xxxx xxxx xxxx uuuu uuuu
UADDR
F5Ch
-000 0000 -000 0000 -uuu uuuu
UEIE
F5Bh
0--0 0000 0--0 0000 u--u uuuu
UEP7
F5Ah
----0 0000 ----0 0000 ----u uuuu
UEP6
F59h
----0 0000 ----0 0000 ----u uuuu
UEP5
F58h
----0 0000 ----0 0000 ----u uuuu
UEP4
F57h
----0 0000 ----0 0000 ----u uuuu
UEP3
F56h
----0 0000 ----0 0000 ----u uuuu
UEP2
F55h
----0 0000 ----0 0000 ----u uuuu
UEP1
F54h
----0 0000 ----0 0000 ----u uuuu
UEP0
F53h
----0 0000 ----0 0000 ----u uuuu
TABLE 23-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register Address
Power-on Reset,
Brown-out Reset
MCLR
Resets,
WDT Reset,
RESET Instruction,
Stack Resets
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hard-
ware stack.
4: See Table 23-3 for Reset value for specific condition.
5: All bits of the ANSELH register initialize to ‘0’ if the PBADEN bit of CONFIG3H is ‘0’.