Datasheet

 2010 Microchip Technology Inc. Preliminary DS41350E-page 245
PIC18F/LF1XK50
21.0 VOLTAGE REFERENCES
There are two independent voltage references
available:
• Programmable Voltage Reference
• 1.024V Fixed Voltage Reference
21.1 Voltage Reference
The Voltage Reference module provides an internally
generated voltage reference for the comparators and
the DAC module. The following features are available:
• Independent from Comparator operation
• Single 32-level voltage ranges
• Output clamped to VSS
• Ratiometric with VDD
• 1.024V Fixed Reference Voltage (FVR)
The REFCON1 register (Register 21-2) controls the
Voltage Reference module shown in Figure 21-1.
21.1.1 INDEPENDENT OPERATION
The voltage reference is independent of the
comparator configuration. Setting the D1EN bit of the
REFCON1 register will enable the voltage reference by
allowing current to flow in the V
REF voltage divider.
When the D1EN bit is cleared, current flow in the V
REF
voltage divider is disabled minimizing the power drain
of the voltage reference peripheral.
21.1.2 OUTPUT VOLTAGE SELECTION
The VREF voltage reference has 32 voltage level
ranges. The 32 levels are set with the DAC1R<4:0>
bits of the REFCON2 register.
The VREF output voltage is determined by the following
equations:
EQUATION 21-1: VREF OUTPUT VOLTAGE
21.1.3 OUTPUT RATIOMETRIC TO V
DD
The comparator voltage reference is VDD derived and
therefore, the V
REF output changes with fluctuations in
V
DD. The tested absolute accuracy of the Comparator
Voltage Reference can be found in Section 27.0
“Electrical Specifications”.
21.1.4 VOLTAGE REFERENCE OUTPUT
The VREF voltage reference can be output to the device
CV
REF pin by setting the DAC1OE bit of the REFCON1
register to ‘1’. Selecting the reference voltage for out-
put on the V
REF pin automatically overrides the digital
output buffer and digital input threshold detector func-
tions of that pin. Reading the CV
REF pin when it has
been configured for reference voltage output will
always return a ‘0’.
Due to the limited current drive capability, a buffer must
be used on the voltage reference output for external
connections to CV
REF. Figure 21-2 shows an example
buffering technique.
21.1.5 OPERATION DURING SLEEP
When the device wakes up from Sleep through an
interrupt or a Watchdog Timer time-out, the contents of
the RECON1 register are not affected. To minimize
current consumption in Sleep mode, the voltage
reference should be disabled.
21.1.6 EFFECTS OF A RESET
A device Reset affects the following:
• Voltage reference is disabled
• Fixed voltage reference is disabled
•V
REF is removed from the CVREF pin
• The DAC1R<4:0> range select bits are cleared
VOUT VSOURCE VSOURCE – x
DAC1R[4:0]
2
5
-------------------------------- V SOURCE+



=
-
IF D1EN = 1
IF D1EN = 0 & D1LPS = 1 & DAC1R[4:0] = 11111:
VOUT VSOURCE =
+
IF D1EN = 0 & D1LPS = 1 & DAC1R[4:0] = 00000:
VOUT VSOURCE =
-
+
-