Datasheet

 2010 Microchip Technology Inc. Preliminary DS41350E-page 205
PIC18F/LF1XK50
TABLE 16-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
16.4.2 SYNCHRONOUS SLAVE MODE
The following bits are used to configure the EUSART
for Synchronous slave operation:
• SYNC = 1
• CSRC = 0
• SREN = 0 (for transmit); SREN = 1 (for receive)
• CREN = 0 (for transmit); CREN = 1 (for receive)
• SPEN = 1
Setting the SYNC bit of the TXSTA register configures the
device for synchronous operation. Clearing the CSRC bit
of the TXSTA register configures the device as a slave.
Clearing the SREN and CREN bits of the RCSTA register
ensures that the device is in the Transmit mode,
otherwise the device will be configured to receive. Setting
the SPEN bit of the RCSTA register enables the
EUSART. If the RX/DT or TX/CK pins are shared with an
analog peripheral the analog I/O functions must be
disabled by clearing the corresponding ANSEL bits.
RX/DT and TX/CK pin output drivers must be disabled
by setting the corresponding TRIS bits.
16.4.2.1 EUSART Synchronous Slave
Transmit
The operation of the Synchronous Master and Slave
modes are identical (see Section 16.4.1.3
“Synchronous Master Transmission”), except in the
case of the Sleep mode.
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
1. The first character will immediately transfer to
the TSR register and transmit.
2. The second word will remain in TXREG register.
3. The TXIF bit will not be set.
4. After the first character has been shifted out of
TSR, the TXREG register will transfer the second
character to the TSR and the TXIF bit will now be
set.
5. If the PEIE and TXIE bits are set, the interrupt
will wake the device from Sleep and execute the
next instruction. If the GIE bit is also set, the
program will call the Interrupt Service Routine.
16.4.2.2 Synchronous Slave Transmission
Set-up:
1. Set the SYNC and SPEN bits and clear the
CSRC bit. Set the TRIS bits corresponding to
the RX/DT and TX/CK I/O pins.
2. Clear the CREN and SREN bits.
3. If using interrupts, ensure that the GIE and PEIE
bits of the INTCON register are set and set the
TXIE bit.
4. If 9-bit transmission is desired, set the TX9 bit.
5. Enable transmission by setting the TXEN bit.
6. If 9-bit transmission is selected, insert the Most
Significant bit into the TX9D bit.
7. Start transmission by writing the Least
Significant 8 bits to the TXREG register.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL
TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF 285
PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 288
PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 288
IPR1
— ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 288
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 287
RCREG EUSART Receive Register 287
TXSTA CSRC
TX9 TXEN SYNC SENDB BRGH TRMT TX9D 287
BAUDCON ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 287
SPBRGH EUSART Baud Rate Generator Register, High Byte 287
SPBRG EUSART Baud Rate Generator Register, Low Byte 287
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.