Datasheet

PIC18F/LF1XK50
DS41350E-page 16 Preliminary  2010 Microchip Technology Inc.
FIGURE 2-1: PIC
®
MCU CLOCK SOURCE BLOCK DIAGRAM
4 x PLL
FOSC<3:0>
OSC2
OSC1
Sleep
CPU
Peripherals
IDLEN
Postscaler
MUX
MUX
16 MHz
8 MHz
4 MHz
2 MHz
1 MHz
250 kHz
500 kHz
IRCF<2:0>
111
110
101
100
011
010
001
000
31 kHz
31 kHz
LFINTOSC
Internal
Oscillator
Block
Clock
Control
SCS<1:0>
HFINTOSC
16 MHz
0
1
INTSRC
Primary
PIC18F/LF1XK50
Sleep
Sleep
System
Secondary
T1OSCEN
Enable
Oscillator
T1OSI
T1OSO
PCLKEN
PRI_SD
 2
CPU
Divider
0
1
1
0
USBDIV
FOSC<3:0>
Low Speed USB
High Speed USB
PLLEN
SPLLEN
Oscillator
Watchdog
Timer
Oscillator
Fail-Safe
Clock
Two-Speed
Start-up
Clock
00
1x
01