Datasheet

PIC18F1XK50/PIC18LF1XK50
DS41350E-page 12 Preliminary  2010 Microchip Technology Inc.
FIGURE 1-1: PIC18F/LF1XK50 BLOCK DIAGRAM
Instruction
Decode and
Control
PORTA
PORTB
PORTC
RA1
RA0
Data Latch
Data Memory
Address Latch
Data Address<12>
12
Access
BSR
FSR0
FSR1
FSR2
inc/dec
logic
Address
4
12
4
PCH PCL
PCLATH
8
31-Level Stack
Program Counter
PRODLPRODH
8 x 8 Multiply
8
BITOP
8
8
ALU<8>
20
8
8
Table Pointer<21>
inc/dec logic
21
8
Data Bus<8>
Table Latch
8
IR
12
3
ROM Latch
PCLATU
PCU
Note 1: RA3 is only available when MCLR functionality is disabled.
2: OSC1/CLKIN and OSC2/CLKOUT are only available in select oscillator modes and when these pins are not being used
as digital I/O. Refer to Section 2.0 “Oscillator Module” for additional information.
3: PIC18F13K50/PIC18F14K50 only.
EUSARTComparator
MSSP
10-bit
ADC
Timer2Timer1 Timer3Timer0
ECCP1
BOR
Data
EEPROM
W
Instruction Bus <16>
STKPTR
Bank
8
State machine
control signals
Decode
8
8
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
OSC1
(2)
OSC2
(2)
VDD,
Internal
Oscillator
Fail-Safe
Clock Monitor
Precision
Reference
Band Gap
V
SS
MCLR
(1)
Block
LFINTOSC
Oscillator
16 MHz
Oscillator
Single-Supply
Programming
T1OSO
T1OSI
FVR
FVR
FVR
CVREF
Address Latch
Program Memory
Data Latch
CVREF
RA3
RA4
RA5
RB4
RB5
RB6
RB7
RC0
RC1
RC2
RC3
RC4
RC5
RC6
RC7
(512/768 bytes)
VUSB
USB
Module
USB
LDO
(3)
Regulator