Information

 2008-2012 Microchip Technology Inc. DS80411H-page 5
PIC18(L)F1XK50
4. Module: EUSART
4.1 RCIDL Bit
In Asynchronous Receive mode, the RCIDL bit of
the BAUDCON register will properly go low when
the RX input goes low at the leading edge of a Start
bit. If the RX input stays low for less than 1/8
th
of a
bit time, then the Start bit is invalid and the RCIDL
should go high. However, the RCIDL bit will stay
low improperly until a valid Start bit is received.
Work around
When monitoring the RCIDL bit, measure the
length of time between the RCIDL going low and
the RCIF flag going high. If this time is greater than
one character time, then restore the RCIDL bit by
resetting the EUSART module. The EUSART
module is reset when the SPEN bit of the RCSTA
register is cleared.
Affected Silicon Revisions
4.2 OERR Bit
The OERR flag of the RCSTA register is reset only
by clearing the CREN bit of the RCSTA register or
by a device Reset. Clearing the SPEN bit of the
RCSTA register does not clear the OERR flag.
Work around
Clear the OERR flag by clearing the CREN bit
instead of clearing the SPEN bit.
Affected Silicon Revisions
4.3 Asynchronous Mode
In Asynchronous mode when TXEN = 0, the TX/
CK output is improperly driven. All mid-range parts
tri-state the TX/CK pin when TXEN = 0 in
Asynchronous mode.
Work around
None.
Affected Silicon Revisions
5. Module: CPU
5.1 Reset on Wake-up
If a wake from Sleep event occurs during the
execution of a Sleep command, the device may
reset. This Reset will be seen as a Power-on
Reset to the device.
Work around
1. Disable all asynchronous interrupt before going
to Sleep.
2. Make sure the timing of an asynchronous
interrupt will not happen during the execution of
the SLEEP instruction.
Affected Silicon Revisions
6. Module: Timer1 Oscillator
6.1 Operation above 90°C
The Timer1 oscillator does not operate above
90°C.
Work around
None.
Affected Silicon Revisions
7. Module: IOC (Interrupt-on-Change)
7.1 IOC (Interrupt-on-Change) False Wake-up
When IOC is enabled for multiple pins to wake-up
the processor from Sleep, invalid interrupts or
wake-ups may occur.
Work around
Use only one pin as IOC with Sleep.
Affected Silicon Revisions
A6 A7 A8 B0
X
A6 A7 A8 B0
X X
A6 A7 A8 B0
X XXX
A6 A7 A8 B0
X X
A6 A7 A8 B0
X XX
A6 A7 A8 B0
X XXX