Information
PIC18(L)F1XK50
DS80411H-page 4 2008-2012 Microchip Technology Inc.
2. Module: MSSP (Master Synchronous
Serial Port)
2.1 Short First Clock Pulse During SPI
When the SPI clock is configured for Timer2/2
(SSPCON1<3:0> = 0011), the first SPI high time
may be short.
Work around
Option 1: Ensure TMR2 value rolls over to
zero immediately before writing to
SSPBUF.
Option 2: Turn Timer2 off and clear TMR2
before writing SSPBUF. Enable
TMR2 after SSPBUF is written.
Affected Silicon Revisions
2.2 SSPIF is Set Prematurely During SPI
The MSSP interrupt flag bit is set at one-half clock
cycle before it should be, if modes 1 or 3 are used.
This affect can be seen in the following situations:
1. Mode 1: CKP = 0, CKE = 0
2. Mode 3: CKP = 1, CKE = 0
It is most notable if the SPI clock is used at
low-clock speeds. If the user responds to the
interrupt and writes to SSPBUF before the
intended interrupt time, then the WCOL (Write
Collision) bit will be set and the transmission will
not occur. Future transmissions will not occur until
the WCOL bit is cleared.
Work around
Delay at least one-half period length of time before
writing to SSPBUF after the SSPIF is set, if using
modes 1 or 3.
Affected Silicon Revisions
3. Module: System Clocks
3.1 Frequency Instability
HFINTOSC output frequency may have up to 1%
short term frequency instability.
Work around
Use the HS, XT or EC clock modes.
Affected Silicon Revisions
3.2 Frequency Shift on Reset
The internal oscillator module may experience a
±1% frequency shift after a Reset. The frequency
shift is not consistent and could cause the
oscillator to operate outside of the 2%
specification.
Work around
To minimize the chances of experiencing the
frequency shift, the following steps should be
taken:
1. Operate the internal oscillator at 8 MHz or 2
MHz.
2. Use an external pull-up on MCLR
or use internal
MCLR
mode.
3. Disable the Power Reset Timer (PWRT).
4. The bypass capacitor and Voltage Regulator
Capacitor (V
CAP) should be used appropriately
to minimize noise in the device.
Affected Silicon Revisions
A6 A7 A8 B0
X XXX
A6 A7 A8 B0
X XXX
A6 A7 A8 B0
X X
A6 A7 A8 B0
X