Datasheet

PIC18(L)F1XK22
DS41365E-page 82  2009-2011 Microchip Technology Inc.
TABLE 8-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values on
page
ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 256
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF 253
INTCON2 RABPU
INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RABIP 253
IOCA — —IOCA5IOCA4
IOCA3
(2)
IOCA2
IOCA1 IOCA0
256
LATA
— —LATA5
(1)
LATA4
(1)
— LATA2 LATA1 LATA0 256
PORTA
— —
RA5
(1)
RA4
(1)
RA3
(2)
RA2 RA1 RA0 256
SLRCON
— — — — — SLRC SLRB SLRA 256
TRISA — — TRISA5
(1)
TRISA4
(1)
— TRISA2 TRISA1 TRISA0 256
WPUA — —WPUA5WPUA4
WPUA3
(2)
WPUA2 WPUA1 WPUA0 253
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA.
Note 1: RA<5:4> and their associated latch and data direction bits are enabled as I/O pins based on oscillator
configuration; otherwise, they are read as ‘0’.
2: Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0).