Datasheet

 2009-2011 Microchip Technology Inc. DS41365E-page 79
PIC18(L)F1XK22
REGISTER 8-1: PORTA: PORTA REGISTER
U-0 U-0 R/W-x R/W-x R-x R/W-x R/W-x R/W-x
— — RA5 RA4 RA3 RA2 RA1 RA0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 RA<5:0>: PORTA I/O Pin bit
(1)
1 = Port pin is > VIH
0 = Port pin is < VIL
Note 1: The RA3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0).
Otherwise, RA3 reads as ‘0’. This bit is read-only.
REGISTER 8-2: TRISA: PORTA TRI-STATE REGISTER
U-0 U-0 R/W-1 R/W-1 U-1 R/W-1 R/W-1 R/W-1
— — TRISA5 TRISA4 — TRISA2 TRISA1 TRISA0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0’
bit 5-4 TRISA<5:4>: PORTA Tri-State Control bit
(1)
1 = PORTA pin configured as an input (tri-stated)
0 = PORTA pin configured as an output
bit 3 Unimplemented: Read as ‘1’
bit 2-0 TRISA<2:0>: PORTA Tri-State Control bit
(1)
1 = PORTA pin configured as an input (tri-stated)
0 = PORTA pin configured as an output
Note 1: TRISA<5:4> always reads ‘1’ in XT, HS and LP Oscillator modes.