Datasheet

PIC18(L)F1XK22
DS41365E-page 64  2009-2011 Microchip Technology Inc.
For external interrupt events, such as the INT pins or
the PORTB interrupt-on-change, the interrupt latency
will be three to four instruction cycles. The exact
latency is the same for one-cycle or two-cycle
instructions. Individual interrupt flag bits are set,
regardless of the status of their corresponding enable
bits or the global interrupt enable bit.
FIGURE 7-1: PIC18 INTERRUPT LOGIC
Note: Do not use the MOVFF instruction to mod-
ify any of the interrupt control registers
while any interrupt is enabled. Doing so
may cause erratic microcontroller behav-
ior.
TMR0IE
GIEH/GIE
GIEL/PEIE
Wake-up if in
Interrupt to CPU
Vector to Location
0008h
INT2IF
INT2IE
INT2IP
INT1IF
INT1IE
INT1IP
TMR0IF
TMR0IE
TMR0IP
RABIF
RABIE
RABIP
IPEN
TMR0IF
TMR0IP
INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
RABIF
RABIE
RABIP
INT0IF
INT0IE
GIEL/PEIE
Interrupt to CPU
Vector to Location
IPEN
IPEN
0018h
SSPIF
SSPIE
SSPIP
SSPIF
SSPIE
SSPIP
ADIF
ADIE
ADIP
RCIF
RCIE
RCIP
Additional Peripheral Interrupts
ADIF
ADIE
ADIP
High Priority Interrupt Generation
Low Priority Interrupt Generation
RCIF
RCIE
RCIP
Additional Peripheral Interrupts
Idle or Sleep modes
GIEH/GIE
Note 1: The RABIF interrupt also requires the individual pin IOCA and IOCB enable.
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