Datasheet

 2009-2011 Microchip Technology Inc. DS41365E-page 397
PIC18(L)F1XK22
VREFCON2 .............................................................. 242
WDTCON (Watchdog Timer Control) ....................... 268
WPUA (Weak Pull-up PORTA) ................................... 80
WPUB (Weak Pull-up PORTB) ................................... 85
RESET .............................................................................. 303
Reset State of Registers ................................................... 252
Resets....................................................................... 245, 257
Brown-out Reset (BOR) ............................................ 257
Oscillator Start-up Timer (OST) ................................ 257
Power-on Reset (POR) ............................................. 257
Power-up Timer (PWRT) .......................................... 257
RETFIE ............................................................................. 304
RETLW ............................................................................. 304
RETURN ........................................................................... 305
Return Address Stack ......................................................... 26
Return Stack Pointer (STKPTR) ......................................... 27
Revision History ................................................................ 389
RLCF................................................................................. 305
RLNCF .............................................................................. 306
RRCF ................................................................................ 306
RRNCF ............................................................................. 307
S
SCK................................................................................... 133
SDI .................................................................................... 133
SDO .................................................................................. 133
SEC_IDLE Mode............................................................... 232
SEC_RUN Mode............................................................... 230
Serial Clock, SCK ............................................................. 133
Serial Data In (SDI)........................................................... 133
Serial Data Out (SDO) ...................................................... 133
Serial Peripheral Interface. See SPI Mode.
SETF................................................................................. 307
Shoot-through Current ...................................................... 126
Single-Supply ICSP Programming.
Slave Select (SS
).............................................................. 133
Slave Select Synchronization ........................................... 139
SLEEP .............................................................................. 308
Sleep Mode....................................................................... 231
SLRCON Register............................................................... 94
Software Simulator (MPLAB SIM)..................................... 325
SPBRG ............................................................................. 187
SPBRGH........................................................................... 187
Special Event Trigger........................................................ 207
Special Event Trigger. See Compare (ECCP Mode).
Special Features of the CPU ............................................ 257
Special Function Registers ................................................. 35
Map............................................................................. 36
SPI Mode
Typical Master/Slave Connection ............................. 137
SPI Mode (MSSP)
Associated Registers ................................................ 141
Bus Mode Compatibility ............................................ 141
Effects of a Reset...................................................... 141
Enabling SPI I/O ....................................................... 137
Master Mode ............................................................. 138
Operation .................................................................. 136
Operation in Power Managed Modes ....................... 141
Serial Clock............................................................... 133
Serial Data In ............................................................ 133
Serial Data Out ......................................................... 133
Slave Mode ............................................................... 139
Slave Select .............................................................. 133
Slave Select Synchronization ................................... 139
SPI Clock .................................................................. 138
Typical Connection ................................................... 137
SR Latch........................................................................... 235
Associated Registers ................................................ 237
SRCON0 Register ............................................................ 236
SRCON1 Register ............................................................ 237
SS
..................................................................................... 133
SSP
Typical SPI Master/Slave Connection ...................... 137
SSPADD Register............................................................. 153
SSPCON1 Register .................................................. 135, 144
SSPCON2 Register .......................................................... 145
SSPMSK Register ............................................................ 152
SSPOV ............................................................................. 165
SSPOV Status Flag .......................................................... 165
SSPSTAT Register ................................................... 134, 143
R/W
Bit ............................................................. 146, 147
Stack Full/Underflow Resets............................................... 28
Standard Instructions........................................................ 273
STATUS Register ............................................................... 40
STKPTR Register ............................................................... 27
SUBFSR ........................................................................... 319
SUBFWB .......................................................................... 308
SUBLW............................................................................. 309
SUBULNK......................................................................... 319
SUBWF............................................................................. 309
SUBWFB .......................................................................... 310
SWAPF............................................................................. 310
T
T0CON Register ................................................................. 95
T1CON Register ................................................................. 99
T2CON Register ............................................................... 105
T3CON Register ............................................................... 107
Table Pointer Operations (table)......................................... 50
Table Reads/Table Writes .................................................. 28
TBLRD.............................................................................. 311
TBLWT ............................................................................. 312
Thermal Considerations.................................................... 344
Time-out in Various Situations (table)............................... 249
Timer0 ................................................................................ 95
Associated Registers .................................................. 97
Operation.................................................................... 96
Overflow Interrupt ....................................................... 97
Prescaler .................................................................... 97
Prescaler Assignment (PSA Bit)................................. 97
Prescaler Select (T0PS2:T0PS0 Bits) ........................ 97
Prescaler. See Prescaler, Timer0.
Reads and Writes in 16-Bit Mode............................... 96
Source Edge Select (T0SE Bit) .................................. 96
Source Select (T0CS Bit) ........................................... 96
Specifications ........................................................... 352
Switching Prescaler Assignment ................................ 97
Timer1 ................................................................................ 99
16-Bit Read/Write Mode ........................................... 102
Associated Registers ................................................ 104
Interrupt .................................................................... 103
Modes of Operation .................................................. 102
Operation.................................................................. 100
Oscillator............................................................. 99, 102
Overflow Interrupt ....................................................... 99
Resetting, Using the CCP Special Event Trigger ..... 103
Specifications ........................................................... 352
TMR1H Register......................................................... 99
TMR1L Register ......................................................... 99
Use as a Real-Time Clock ........................................ 103
Timer2 .............................................................................. 105
Associated Registers ................................................ 106