Datasheet

 2009-2011 Microchip Technology Inc. DS41365E-page 393
PIC18(L)F1XK22
Details on Individual Family Members .......................... 8
Features (20-Pin Devices) ............................................ 9
New Core Features....................................................... 7
Other Special Features................................................. 8
Device Reset Timers......................................................... 249
Oscillator Start-up Timer (OST) ................................ 249
PLL Lock Time-out.................................................... 249
Power-up Timer (PWRT) .......................................... 249
Time-out Sequence................................................... 249
DEVID1 Register............................................................... 266
DEVID2 Register............................................................... 266
Direct Addressing................................................................ 42
E
ECCPAS Register............................................................. 123
EECON1 Register......................................................... 49, 58
Effect on Standard PIC Instructions .................................. 320
Electrical Specifications .................................................... 327
Enhanced Capture/Compare/PWM (ECCP) ..................... 111
Associated Registers ................................................ 131
Enhanced PWM Mode .............................................. 115
Auto-Restart...................................................... 125
Auto-shutdown.................................................. 123
Direction Change in Full-Bridge Output Mode .. 121
Full-Bridge Application ...................................... 119
Full-Bridge Mode .............................................. 119
Half-Bridge Application ..................................... 118
Half-Bridge Application Examples .................... 126
Half-Bridge Mode.............................................. 118
Output Relationships (Active-High and
Active-Low) ............................................... 116
Output Relationships Diagram .......................... 117
Programmable Dead Band Delay ..................... 126
Shoot-through Current ...................................... 126
Start-up Considerations .................................... 122
Outputs and Configuration ........................................ 112
Specifications............................................................ 353
Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART)............................... 175
Errata .................................................................................... 6
EUSART ........................................................................... 175
Asynchronous Mode ................................................. 177
12-bit Break Transmit and Receive .................. 194
Associated Registers, Receive ......................... 183
Associated Registers, Transmit ........................ 179
Auto-Wake-up on Break ................................... 192
Baud Rate Generator (BRG) ............................ 187
Clock Accuracy ................................................. 184
Receiver............................................................ 180
Setting up 9-bit Mode with Address Detect....... 182
Transmitter........................................................ 177
Baud Rate Generator (BRG)
Associated Registers ........................................ 187
Auto Baud Rate Detect ..................................... 191
Baud Rate Error, Calculating ............................ 187
Baud Rates, Asynchronous Modes .................. 188
Formulas ........................................................... 187
High Baud Rate Select (BRGH Bit) .................. 187
Clock polarity
Synchronous Mode........................................... 195
Data polarity
Asynchronous Receive ..................................... 180
Asynchronous Transmit .................................... 177
Synchronous Mode........................................... 195
Interrupts
Asynchronous Receive ..................................... 181
Asynchronous Transmit.................................... 177
Synchronous Master Mode............................... 195, 200
Associated Registers, Receive......................... 199
Associated Registers, Transmit................ 197, 200
Reception ......................................................... 197
Transmission .................................................... 195
Synchronous Slave Mode
Associated Registers, Receive......................... 201
Reception ......................................................... 201
Transmission .................................................... 200
Extended Instruction Set
ADDFSR................................................................... 316
ADDULNK ................................................................ 316
and Using MPLAB Tools .......................................... 322
CALLW ..................................................................... 317
Considerations for Use ............................................. 320
MOVSF..................................................................... 317
MOVSS..................................................................... 318
PUSHL...................................................................... 318
SUBFSR ................................................................... 319
SUBULNK................................................................. 319
Syntax....................................................................... 315
F
Fail-Safe Clock Monitor .............................................. 23, 257
Fail-Safe Condition Clearing....................................... 23
Fail-Safe Detection ..................................................... 23
Fail-Safe Operation .................................................... 23
Reset or Wake-up from Sleep .................................... 23
Fast Register Stack ............................................................ 28
Firmware Instructions ....................................................... 273
Flash Program Memory ...................................................... 47
Associated Registers .................................................. 55
Control Registers........................................................ 48
EECON1 and EECON2 ...................................... 48
TABLAT (Table Latch) Register ......................... 50
TBLPTR (Table Pointer) Register....................... 50
Erase Sequence ......................................................... 52
Erasing ....................................................................... 52
Operation During Code-Protect .................................. 55
Reading ...................................................................... 51
Table Pointer
Boundaries Based on Operation ........................ 50
Table Pointer Boundaries ........................................... 50
Table Reads and Table Writes ................................... 47
Write Sequence .......................................................... 53
Writing To ................................................................... 53
Protection Against Spurious Writes .................... 55
Unexpected Termination .................................... 55
Write Verify ......................................................... 55
G
General Call Address Support .......................................... 158
GOTO ............................................................................... 294
H
Hardware Multiplier............................................................. 61
Introduction................................................................. 61
Operation.................................................................... 61
Performance Comparison........................................... 61
I
I/O Ports ............................................................................. 77
I
2
C
Associated Registers ................................................ 174
I
2
C Mode (MSSP)