Datasheet

 2009-2011 Microchip Technology Inc. DS41365E-page 39
PIC18(L)F1XK22
SPBRGH EUSART Baud Rate Generator Register, High Byte 0000 0000 255, 187
SPBRG EUSART Baud Rate Generator Register, Low Byte 0000 0000 255, 187
RCREG EUSART Receive Register 0000 0000 255, 185
TXREG EUSART Transmit Register 0000 0000 255, 184
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 255, 184
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 255, 185
EEADR EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 255, 47,
57
EEDATA EEPROM Data Register 0000 0000 255, 47,
57
EECON2 EEPROM Control Register 2 (not a physical register) 0000 0000 255, 47,
57
EECON1 EEPGD CFGS
— FREE WRERR WREN WR RD xx-0 x000 255, 47,
57
IPR2
OSCFIP C1IP C2IP EEIP BCLIP
—
TMR3IP
— 1111 111- 256, 73
PIR2
OSCFIF C1IF C2IF EEIF BCLIF
—
TMR3IF
— 0000 000- 256, 69
PIE2
OSCFIE C1IE C2IE EEIE BCLIE
—
TMR3IE
— 0000 000- 256, 71
IPR1
—
ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP
-111 1111 256, 72
PIR1
—
ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF
-000 0000 256, 68
PIE1 —
ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE
-000 0000 256, 70
OSCTUNE INTSRC PLLEN TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 0000 0000 20, 256
TRISC
TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
1111 1111 256, 88
TRISB
TRISB7 TRISB6 TRISB5 TRISB4
— — — — 1111 ---- 256, 84
TRISA — —
TRISA5 TRISA4
—
TRISA2 TRISA1 TRISA0
--11 -111 256, 79
LATC
LATC 7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0
xxxx xxxx 256, 89
LATB
LATB7 LATB6 LATB5 LATB4
— — — — xxxx ---- 256, 85
LATA — —
LATA5 LATA4
—
LATA2 LATA1 LATA0
--xx -xxx 256, 80
PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx 256, 88
PORTB
RB7RB6RB5RB4
— — — — xxxx ---- 256, 84
PORTA
— —
RA5 RA4 RA3
(2)
RA2 RA1 RA0
--xx xxxx 256, 79
ANSELH
— — — — ANS11 ANS10 ANS9 ANS8 ---- 1111 256, 93
ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 256, 92
IOCB IOCB7 IOCB6 IOCB5 IOCB4
— — — — 0000 ---- 256, 85
IOCA
— — IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCA0 --00 0000 256, 80
WPUB WPUB7 WPUB6 WPUB5 WPUB4
— — — — 1111 ---- 256, 85
WPUA
— —
WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0
--11 1111 253, 80
SLRCON
— — — — — SLRC SLRB SLRA ---- -111 256, 94
SSPMSK MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 1111 1111 256, 152
CM1CON0
C1ON C1OUT C1OE C1POL C1SP C1R C1CH1 C1CH0 0000 1000 256, 223
CM2CON1
MC1OUT MC2OUT C1RSEL C2RSEL C1HYS C2HYS C1SYNC C2SYNC 0000 0000 256, 224
CM2CON0
C2ON C2OUT C2OE C2POL C2SP C2R C2CH1 C2CH0 0000 1000 256, 224
SRCON1
SRSPE SRSCKE SRSC2E SRSC1E SRRPE SRRCKE SRRC2E SRRC1E 0000 0000 256, 237
SRCON0
SRLEN SRCLK2 SRCLK1 SRCLK0 SRQEN SRNQEN SRPS SRPR 0000 0000 256, 236
TABLE 3-2: REGISTER FILE SUMMARY (PIC18(L)F1XK22) (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Details
on
page:
Legend: x = unknown, u = unchanged, — = unimplemented, q = value depends on condition
Note 1: The SBOREN bit is only available when the BOREN<1:0> Configuration bits = 01; otherwise it is disabled and reads as ‘0’. See
Section 21.4 “Brown-out Reset (BOR)”.
2: The RA3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0). Otherwise, RA3 reads as ‘0’. This bit is
read-only.