Datasheet
2009-2011 Microchip Technology Inc. DS41365E-page 37
PIC18(L)F1XK22
TABLE 3-2: REGISTER FILE SUMMARY (PIC18(L)F1XK22)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Details
on
page:
TOSU
— — — Top-of-Stack Upper Byte (TOS<20:16>) ---0 0000 253, 26
TOSH Top-of-Stack, High Byte (TOS<15:8>) 0000 0000 253, 26
TOSL Top-of-Stack, Low Byte (TOS<7:0>) 0000 0000 253, 26
STKPTR STKOVF STKUNF
— SP4 SP3 SP2 SP1 SP0 00-0 0000 253, 27
PCLATU
— — — Holding Register for PC<20:16> ---0 0000 253, 26
PCLATH Holding Register for PC<15:8> 0000 0000 253, 26
PCL PC, Low Byte (PC<7:0>) 0000 0000 253, 26
TBLPTRU
— — — Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) ---0 0000 253, 50
TBLPTRH Program Memory Table Pointer, High Byte (TBLPTR<15:8>) 0000 0000 253, 50
TBLPTRL Program Memory Table Pointer, Low Byte (TBLPTR<7:0>) 0000 0000 253, 50
TABLAT Program Memory Table Latch 0000 0000 253, 50
PRODH Product Register, High Byte xxxx xxxx 253, 61
PRODL Product Register, Low Byte xxxx xxxx 253, 61
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF 0000 000x 253, 65
INTCON2 RABPU
INTEDG0 INTEDG1 INTEDG2 —TMR0IP— RABIP 1111 -1-1 253, 66
INTCON3 INT2IP INT1IP
— INT2IE INT1IE — INT2IF INT1IF 11-0 0-00 253, 67
INDF0 Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register) N/A 253, 42
POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register) N/A 253, 42
POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register) N/A 253, 42
PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) N/A 253, 42
PLUSW0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) – value
of FSR0 offset by W
N/A 253, 42
FSR0H
— — — — Indirect Data Memory Address Pointer 0, High Byte ---- 0000 253, 42
FSR0L Indirect Data Memory Address Pointer 0, Low Byte xxxx xxxx 253, 42
WREG Working Register xxxx xxxx 253
INDF1 Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register) N/A 253, 42
POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register) N/A 253, 42
POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register) N/A 253, 42
PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) N/A 253, 42
PLUSW1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) – value
of FSR1 offset by W
N/A 253, 42
FSR1H
— — — — Indirect Data Memory Address Pointer 1, High Byte ---- 0000 254, 42
FSR1L Indirect Data Memory Address Pointer 1, Low Byte xxxx xxxx 254, 42
BSR
— — — — Bank Select Register ---- 0000 254, 31
INDF2 Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register) N/A 254, 42
POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register) N/A 254, 42
POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register) N/A 254, 42
PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) N/A 254, 42
PLUSW2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) – value
of FSR2 offset by W
N/A 254, 42
FSR2H
— — — — Indirect Data Memory Address Pointer 2, High Byte ---- 0000 254, 42
FSR2L Indirect Data Memory Address Pointer 2, Low Byte xxxx xxxx 254, 42
STATUS
— — —N OV Z DCC---x xxxx 254, 40
Legend: x = unknown, u = unchanged, — = unimplemented, q = value depends on condition
Note 1: The SBOREN bit is only available when the BOREN<1:0> Configuration bits = 01; otherwise it is disabled and reads as ‘0’. See
Section 21.4 “Brown-out Reset (BOR)”.
2: The RA3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0). Otherwise, RA3 reads as ‘0’. This bit is
read-only.