Datasheet

PIC18(L)F1XK22
DS41365E-page 268  2009-2011 Microchip Technology Inc.
22.2.1 CONTROL REGISTER
Register 22-14 shows the WDTCON register. This is a
readable and writable register which contains a control
bit that allows software to override the WDT enable
Configuration bit, but only if the Configuration bit has
disabled the WDT.
TABLE 22-2: SUMMARY OF WATCHDOG TIMER REGISTERS
22.3 Program Verification and
Code Protection
The overall structure of the code protection on the
PIC18 Flash devices differs significantly from other
PIC
®
microcontroller devices.
The user program memory is divided into five blocks.
One of these is a boot block of 0.5K or 2K bytes,
depending on the device. The remainder of the mem-
ory is divided into individual blocks on binary boundar-
ies.
Each of the five blocks has three code protection bits
associated with them. They are:
• Code-Protect bit (CPn)
• Write-Protect bit (WRTn)
• External Block Table Read bit (EBTRn)
Figure 22-2 shows the program memory organization
for 8, 16 and 32-Kbyte devices and the specific code
protection bit associated with each block. The actual
locations of the bits are summarized in Table 22-3.
REGISTER 22-14: WDTCON: WATCHDOG TIMER CONTROL REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
— — — — — — —SWDTEN
(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-1 Unimplemented: Read as ‘0’
bit 0 SWDTEN: Software Enable or Disable the Watchdog Timer bit
(1)
1 = WDT is turned on
0 = WDT is turned off (Reset value)
Note 1: This bit has no effect if the Configuration bit, WDTEN, is enabled.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
CONFIG2H — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN 261
RCON
IPEN SBOREN — RI TO PD POR BOR 254
WDTCON — — — — — — —SWDTEN254
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Watchdog Timer.