Datasheet

 2009-2011 Microchip Technology Inc. DS41365E-page 255
PIC18(L)F1XK22
ADRESH
FC4h
xxxx xxxx uuuu uuuu uuuu uuuu
ADRESL
FC3h
xxxx xxxx uuuu uuuu uuuu uuuu
ADCON0
FC2h
--00 0000 --00 0000 --uu uuuu
ADCON1
FC1h
---- 0000 ---- 0000 ---- uuuu
ADCON2
FC0h
0-00 0000 0-00 0000 u-uu uuuu
CCPR1H
FBFh
xxxx xxxx uuuu uuuu uuuu uuuu
CCPR1L
FBEh
xxxx xxxx uuuu uuuu uuuu uuuu
CCP1CON
FBDh
0000 0000 0000 0000 uuuu uuuu
VREFCON2
FBCh
---0 0000 ---0 0000 ---u uuuu
VREFCON1
FBBh
000- 00-0 000- 00-0 uuu- uu-u
VREFCON0
FBAh
0001 00-- 0001 00-- uuuu uu--
PSTRCON
FB9h
---0 0001 ---0 0001 ---u uuuu
BAUDCON
FB8h
0100 0-00 0100 0-00 uuuu u-uu
PWM1CON
FB7h
0000 0000 0000 0000 uuuu uuuu
ECCP1AS
FB6h
0000 0000 0000 0000 uuuu uuuu
TMR3H
FB3h
xxxx xxxx uuuu uuuu uuuu uuuu
TMR3L
FB2h
xxxx xxxx uuuu uuuu uuuu uuuu
T3CON
FB1h
0000 0000 uuuu uuuu uuuu uuuu
SPBRGH
FB0h
0000 0000 0000 0000 uuuu uuuu
SPBRG
FAFh
0000 0000 0000 0000 uuuu uuuu
RCREG
FAEh
0000 0000 0000 0000 uuuu uuuu
TXREG
FADh
0000 0000 0000 0000 uuuu uuuu
TXSTA
FACh
0000 0010 0000 0010 uuuu uuuu
RCSTA
FABh
0000 000x 0000 000x uuuu uuuu
EEADR
FAAh
0000 0000 0000 0000 uuuu uuuu
EEDATA
FA8h
0000 0000 0000 0000 uuuu uuuu
EECON2
FA7h
0000 0000 0000 0000 0000 0000
EECON1
FA6h
xx-0 x000 uu-0 u000 uu-0 u000
TABLE 21-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register Address
Power-on Reset,
Brown-out Reset
MCLR
Resets,
WDT Reset,
RESET Instruction,
Stack Resets
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hard-
ware stack.
4: See Table 21-3 for Reset value for specific condition.