Datasheet

 2009-2011 Microchip Technology Inc. DS41365E-page 253
PIC18(L)F1XK22
TABLE 21-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS
Register Address
Power-on Reset,
Brown-out Reset
MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets
Wake-up via WDT
or Interrupt
TOSU FFFh
---0 0000 ---0 0000 ---0 uuuu
(3)
TOSH
FFEh
0000 0000 0000 0000 uuuu uuuu
(3)
TOSL
FFDh
0000 0000 0000 0000 uuuu uuuu
(3)
STKPTR
FFCh
00-0 0000 uu-0 0000 uu-u uuuu
(3)
PCLATU
FFBh
---0 0000 ---0 0000 ---u uuuu
PCLATH
FFAh
0000 0000 0000 0000 uuuu uuuu
PCL
FF9h
0000 0000 0000 0000 PC + 2
(2)
TBLPTRU
FF8h
---0 0000 ---0 0000 ---u uuuu
TBLPTRH
FF7h
0000 0000 0000 0000 uuuu uuuu
TBLPTRL
FF6h
0000 0000 0000 0000 uuuu uuuu
TABLAT
FF5h
0000 0000 0000 0000 uuuu uuuu
PRODH
FF4h
xxxx xxxx uuuu uuuu uuuu uuuu
PRODL
FF3h
xxxx xxxx uuuu uuuu uuuu uuuu
INTCON
FF2h
0000 000x 0000 000u uuuu uuuu
(1)
INTCON2
FF1h
1111 -1-1 1111 -1-1 uuuu -u-u
(1)
INTCON3
FF0h
11-0 0-00 11-0 0-00 uu-u u-uu
(1)
INDF0
FEFh
N/A N/A N/A
POSTINC0
FEEh
N/A N/A N/A
POSTDEC0
FEDh
N/A N/A N/A
PREINC0
FECh
N/A N/A N/A
PLUSW0
FEBh
N/A N/A N/A
FSR0H
FEAh
---- 0000 ---- 0000 ---- uuuu
FSR0L
FE9h
xxxx xxxx uuuu uuuu uuuu uuuu
WREG
FE8h
xxxx xxxx uuuu uuuu uuuu uuuu
INDF1
FE7h
N/A N/A N/A
POSTINC1
FE6h
N/A N/A N/A
POSTDEC1
FE5h
N/A N/A N/A
PREINC1
FE4h
N/A N/A N/A
PLUSW1
FE3h
N/A N/A N/A
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hard-
ware stack.
4: See Table 21-3 for Reset value for specific condition.