Datasheet

 2009-2011 Microchip Technology Inc. DS41365E-page 249
PIC18(L)F1XK22
21.5 Device Reset Timers
PIC18(L)F1XK22 devices incorporate three separate
on-chip timers that help regulate the Power-on Reset
process. Their main function is to ensure that the
device clock is stable before code is executed. These
timers are:
• Power-up Timer (PWRT)
• Oscillator Start-up Timer (OST)
• PLL Lock Time-out
21.5.1 POWER-UP TIMER (PWRT)
The Power-up Timer (PWRT) of PIC18(L)F1XK22
devices is an 11-bit counter which uses the LFIN-
TOSC source as the clock input. This yields an
approximate time interval of 2048 x 32 s=65.6ms.
While the PWRT is counting, the device is held in
Reset.
The power-up time delay depends on the LFINTOSC
clock and will vary from chip-to-chip due to temperature
and process variation. See Section 25.0 “Electrical
Specifications” for details.
The PWRT is enabled by clearing the PWRTEN
Configuration bit.
21.5.2 OSCILLATOR START-UP TIMER
(OST)
The Oscillator Start-up Timer (OST) provides a 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over. This ensures that the crystal
oscillator or resonator has started and stabilized.
The OST time-out is invoked only for XT, LP, HS and
HSPLL modes and only on Power-on Reset, or on exit
from all power-managed modes that stop the external
oscillator.
21.5.3 PLL LOCK TIME-OUT
With the PLL enabled in its PLL mode, the time-out
sequence following a Power-on Reset is slightly
different from other oscillator modes. A separate timer
is used to provide a fixed time-out that is sufficient for
the PLL to lock to the main oscillator frequency. This
PLL lock time-out (T
PLL) is typically 2ms and follows the
oscillator start-up time-out.
21.5.4 TIME-OUT SEQUENCE
On power-up, the time-out sequence is as follows:
1. After the POR pulse has cleared, PWRT time-out
is invoked (if enabled).
2. Then, the OST is activated.
The total time-out will vary based on oscillator
configuration and the status of the PWRT. Figure 21-3,
Figure 21-4, Figure 21-5, Figure 21-6 and Figure 21-7
all depict time-out sequences on power-up, with the
Power-up Timer enabled and the device operating in
HS Oscillator mode. Figures 21-3 through 21-6 also
apply to devices operating in XT or LP modes. For
devices in RC mode and with the PWRT disabled, on
the other hand, there will be no time-out at all.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, all time-outs will expire, after
which, bringing MCLR
high will allow program
execution to begin immediately (Figure 21-5). This is
useful for testing purposes or to synchronize more than
one PIC18(L)F1XK22 device operating in parallel.
TABLE 21-2: TIME-OUT IN VARIOUS SITUATIONS
Oscillator
Configuration
Power-up
(2)
and Brown-out
Exit from
Power-Managed Mode
PWRTEN
= 0 PWRTEN = 1
HSPLL 66 ms
(1)
+ 1024 TOSC + 2 ms
(2)
1024 TOSC + 2 ms
(2)
1024 TOSC + 2 ms
(2)
HS, XT, LP 66 ms
(1)
+ 1024 TOSC 1024 TOSC 1024 TOSC
EC, ECIO 66 ms
(1)
——
RC, RCIO 66 ms
(1)
——
INTIO1, INTIO2 66 ms
(1)
——
Note 1: 66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay.
2: 2 ms is the nominal time required for the PLL to lock.