Datasheet

 2009-2011 Microchip Technology Inc. DS41365E-page 239
PIC18(L)F1XK22
20.0 VOLTAGE REFERENCES
There are two independent voltage references
available:
• Programmable Voltage Reference
• 1.024V Fixed Voltage Reference
20.1 Voltage Reference
The voltage reference module provides an internally
generated voltage reference for the comparators and
the DAC module. The following features are available:
• Independent from comparator operation
• Single 32-level voltage ranges
• Output clamped to VSS
• Ratiometric with VDD
• 1.024V Fixed Voltage Reference (FVR)
The VREFCON1 register (Register 20-2) controls the
Voltage Reference module shown in Figure 20-1.
20.1.1 INDEPENDENT OPERATION
The voltage reference is independent of the
comparator configuration. Setting the D1EN bit of the
VREFCON1 register will enable the voltage reference
by allowing current to flow in the V
REF voltage divider.
When the D1EN bit is cleared, current flow in the V
REF
voltage divider is disabled minimizing the power drain
of the voltage reference peripheral.
20.1.2 OUTPUT VOLTAGE SELECTION
The VREF voltage reference has 32 voltage level
ranges. The 32 levels are set with the DAC1R<4:0>
bits of the VREFCON2 register.
The VREF output voltage is determined by the following
equations:
EQUATION 20-1: VREF OUTPUT VOLTAGE
20.1.3 OUTPUT RATIOMETRIC TO VDD
The comparator voltage reference is VDD derived and
therefore, the V
REF output changes with fluctuations in
V
DD. The tested absolute accuracy of the Comparator
Voltage Reference can be found in Section 25.0
“Electrical Specifications”.
20.1.4 VOLTAGE REFERENCE OUTPUT
The VREF voltage reference can be output to the device
CV
REF pin by setting the DAC1OE bit of the
VREFCON1 register to ‘1’. Selecting the reference volt-
age for output on the VREF pin automatically overrides
the digital output buffer and digital input threshold
detector functions of that pin. Reading the CVREF pin
when it has been configured for reference voltage out-
put will always return a ‘0’.
Due to the limited current drive capability, a buffer must
be used on the voltage reference output for external
connections to CV
REF. Figure 20-2 shows an example
buffering technique.
20.1.5 OPERATION DURING SLEEP
When the device wakes up from Sleep through an
interrupt or a Watchdog Timer time-out, the contents of
the RECON1 register are not affected. To minimize
current consumption in Sleep mode, the voltage
reference should be disabled.
20.1.6 EFFECTS OF A RESET
A device Reset affects the following:
• Voltage reference is disabled
• Fixed voltage reference is disabled
•VREF is removed from the CVREF pin
• The DAC1R<4:0> range select bits are cleared
VOUT VSOURCE VSOURCE – x
DAC1R[4:0]
2
5
-------------------------------- V SOURCE+



=
-
IF D1EN = 1
IF D1EN = 0 & D1LPS = 1 & DAC1R[4:0] = 11111:
VOUT VSOURCE =
+
IF D1EN = 0 & D1LPS = 1 & DAC1R[4:0] = 00000:
VOUT VSOURCE =
-
+
-