Datasheet

PIC18(L)F1XK22
DS41365E-page 236  2009-2011 Microchip Technology Inc.
TABLE 19-1: SRCLK FREQUENCY TABLE
SRCLK Divider F
OSC = 20 MHz FOSC = 16 MHz FOSC = 8 MHz FOSC = 4 MHz FOSC = 1 MHz
111 512 25.6 s 32 s64 s 128 s 512 s
110 256 12.8 s 16 s32 s64 s 256 s
101 128 6.4 s8 s16 s32 s 128 s
100 64 3.2 s4 s8 s16 s64 s
011 32 1.6 s2 s4 s8 s32 s
010 16 0.8 s1 s2 s4 s16 s
001 80.4 s0.5 s1 s2 s8 s
000 40.2 s0.25 s0.5 s1 s4 s
REGISTER 19-1: SRCON0: SR LATCH CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SRLEN SRCLK2 SRCLK1 SRCLK0 SRQEN SRNQEN SRPS SRPR
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented C = Clearable only bit
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 SRLEN: SR Latch Enable bit
(1)
1 = SR latch is enabled
0 = SR latch is disabled
bit 6-4 SRCLK<2:0>
(1)
: SR Latch Clock divider bits
000 = 1/4 Peripheral cycle clock
001 = 1/8 Peripheral cycle clock
010 = 1/16 Peripheral cycle clock
011 = 1/32 Peripheral cycle clock
100 = 1/64 Peripheral cycle clock
101 = 1/128 Peripheral cycle clock
110 = 1/256 Peripheral cycle clock
111 = 1/512 Peripheral cycle clock
bit 3 SRQEN: SR Latch Q Output Enable bit
1 = Q is present on the RA2 pin
0 = Q is internal only
bit 2 SRNQEN: SR Latch Q
Output Enable bit
1 =Q
is present on the RC4 pin
0 =Q
is internal only
bit 1 SRPS: Pulse Set Input of the SR Latch bit
1 = Pulse input
0 = Always reads back ‘0’
bit 0 SRPR: Pulse Reset Input of the SR Latch bit
1 = Pulse input
0 = Always reads back ‘0’
Note 1: Changing the SRCLK bits while the SR latch is enabled may cause false triggers to the set and Reset
inputs of the latch.