Datasheet

PIC18(L)F1XK22
DS41365E-page 234  2009-2011 Microchip Technology Inc.
18.5.3 EXIT BY RESET
Exiting Sleep and Idle modes by Reset causes code
execution to restart at address 0. See Section 21.0
“Reset” for more details.
The exit delay time from Reset to the start of code
execution depends on both the clock sources before
and after the wake-up and the type of oscillator. Exit
delays are summarized in Table 18-2.
18.5.4 EXIT WITHOUT AN OSCILLATOR
START-UP DELAY
Certain exits from power-managed modes do not
invoke the OST at all. There are two cases:
• PRI_IDLE mode, where the primary clock source
is not stopped and
• the primary clock source is not any of the LP, XT,
HS or HSPLL modes.
In these instances, the primary clock source either
does not require an oscillator start-up delay since it is
already running (PRI_IDLE), or normally does not
require an oscillator start-up delay (RC, EC, INTOSC,
and INTOSCIO modes). However, a fixed delay of
interval T
CSD following the wake event is still required
when leaving Sleep and Idle modes to allow the CPU
to prepare for execution. Instruction execution resumes
on the first clock cycle following this delay.
TABLE 18-2: EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE
(BY CLOCK SOURCES)
Clock Source
before Wake-up
Clock Source
after Wake-up
Exit Delay
Clock Ready Status
Bit (OSCCON)
Primary Device Clock
(PRI_IDLE mode)
LP, XT, HS
T
CSD
(1)
OSTSHSPLL
EC, RC
HFINTOSC
(2)
IOSF
T1OSC or LFINTOSC
(1)
LP, XT, HS TOST
(3)
OSTSHSPLL TOST + t
PLL
(3)
EC, RC TCSD
(1)
HFINTOSC
(1)
TIOBST
(4)
IOSF
HFINTOSC
(2)
LP, XT, HS TOST
(4)
OSTSHSPLL TOST + t
PLL
(3)
EC, RC TCSD
(1)
HFINTOSC
(1)
None IOSF
None
(Sleep mode)
LP, XT, HS T
OST
(3)
OSTSHSPLL TOST + t
PLL
(3)
EC, RC TCSD
(1)
HFINTOSC
(1)
TIOBST
(4)
IOSF
Note 1: TCSD is a required delay when waking from Sleep and all Idle modes and runs concurrently with any other
required delays (see Section 18.4 “Idle Modes”). On Reset, HFINTOSC defaults to 1 MHz.
2: Includes both the HFINTOSC 16 MHz source and postscaler derived frequencies.
3: T
OST is the Oscillator Start-up Timer. t
PLL
is the PLL Lock-out Timer (parameter F12).
4: Execution continues during the HFINTOSC stabilization period, T
IOBST.