Datasheet

 2009-2011 Microchip Technology Inc. DS41365E-page 219
PIC18(L)F1XK22
FIGURE 17-3: COMPARATOR C2 SIMPLIFIED BLOCK DIAGRAM
MUX
C2
C2POL
C2OUT
To PWM Logic
0
1
2
3
C2ON
(1)
C2CH<1:0>
2
DQ
EN
DQ
EN
CL
RD_CM2CON0
Q3*RD_CM2CON0
Q1
Set C2IF
To
NRESET
C2V
IN-
C2V
IN+
C2OUT pin
C12IN0-
C12IN1-
C12IN2-
C12IN3-
Data Bus
Note 1: When C2ON = 0, the C2 comparator will produce a ‘0’ output to the XOR Gate.
2: Q1 and Q3 are phases of the four-phase system clock (F
OSC).
3: Q1 is held high during Sleep mode.
4: Positive going pulse generated on both falling and rising edges of the bit.
0
1
C2R
MUX
C2IN+
0
1
MUX
VREF
C2RSEL
FVR
C2SP
C2V
REF
0
1
C2SYNC
C20E
DQ
SYNCC2OUT
From TMR1L[0]
(4)