Datasheet

PIC18(L)F1XK22
DS41365E-page 218 2009-2011 Microchip Technology Inc.
FIGURE 17-2: COMPARATOR C1 SIMPLIFIED BLOCK DIAGRAM
Note 1: When C1ON = 0, the C1 comparator will produce a ‘0’ output to the XOR Gate.
2: Q1 and Q3 are phases of the four-phase system clock (F
OSC).
3: Q1 is held high during Sleep mode.
4: Positive going pulse generated on both falling and rising edges of the bit.
MUX
C1
C1POL
C1OUT
To PWM Logic
0
1
2
3
C1ON
(1)
C1CH<1:0>
2
0
1
C1R
MUX
RD_CM1CON0
Set C1IF
To
C1VIN-
C1V
IN+
C12IN0-
C12IN1-
C12IN2-
C12IN3-
C1IN+
DQ
EN
Q1
Data Bus
DQ
EN
CL
Q3*RD_CM1CON0
NReset
+
-
0
1
MUX
VREF
C1RSEL
FVR
C1SP
C1V
REF
C1OE
C1OUT
0
1
C1SYNC
From TMR1L[0]
(4)
DQ
SYNCC1OUT