Datasheet

 2009-2011 Microchip Technology Inc. DS41365E-page 197
PIC18(L)F1XK22
TABLE 15-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
15.4.1.6 Synchronous Master Reception
Data is received at the RX/DT pin. The RX/DT pin
output driver must be disabled by setting the
corresponding TRIS bits when the EUSART is
configured for synchronous master receive operation.
In Synchronous mode, reception is enabled by setting
either the Single Receive Enable bit (SREN of the
RCSTA register) or the Continuous Receive Enable bit
(CREN of the RCSTA register).
When SREN is set and CREN is clear, only as many
clock cycles are generated as there are data bits in a
single character. The SREN bit is automatically cleared
at the completion of one character. When CREN is set,
clocks are continuously generated until CREN is
cleared. If CREN is cleared in the middle of a character
the CK clock stops immediately and the partial charac-
ter is discarded. If SREN and CREN are both set, then
SREN is cleared at the completion of the first character
and CREN takes precedence.
To initiate reception, set either SREN or CREN. Data is
sampled at the RX/DT pin on the trailing edge of the
TX/CK clock pin and is shifted into the Receive Shift
Register (RSR). When a complete character is
received into the RSR, the RCIF bit is set and the
character is automatically transferred to the two
character receive FIFO. The Least Significant eight bits
of the top character in the receive FIFO are available in
RCREG. The RCIF bit remains set as long as there are
unread characters in the receive FIFO.
15.4.1.7 Slave Clock
Synchronous data transfers use a separate clock line,
which is synchronous with the data. A device configured
as a slave receives the clock on the TX/CK line. The
TX/CK pin output driver must be disabled by setting the
associated TRIS bit when the device is configured for
synchronous slave transmit or receive operation. Serial
data bits change on the leading edge to ensure they are
valid at the trailing edge of each clock. One data bit is
transferred for each clock cycle. Only as many clock
cycles should be received as there are data bits.
15.4.1.8 Receive Overrun Error
The receive FIFO buffer can hold two characters. An
overrun error will be generated if a third character, in its
entirety, is received before RCREG is read to access
the FIFO. When this happens the OERR bit of the
RCSTA register is set. Previous data in the FIFO will
not be overwritten. The two characters in the FIFO
buffer can be read, however, no additional characters
will be received until the error is cleared. The OERR bit
can only be cleared by clearing the overrun condition.
If the overrun error occurred when the SREN bit is set
and CREN is clear then the error is cleared by reading
RCREG. If the overrun occurred when the CREN bit is
set then the error condition is cleared by either clearing
the CREN bit of the RCSTA register or by clearing the
SPEN bit which resets the EUSART.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
BAUDCON
ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 255
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF 253
IPR1 — ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 256
PIE1
— ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 256
PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 256
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 255
SPBRG EUSART Baud Rate Generator Register, Low Byte 255
SPBRGH EUSART Baud Rate Generator Register, High Byte 255
TRISC TRISC7 TRISC6
TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 256
TXREG EUSART Transmit Register 255
TXSTA CSRC TX9 TXEN SYNC
SENDB BRGH TRMT TX9D 255
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.