Datasheet

PIC18(L)F1XK22
DS41365E-page 176 2009-2011 Microchip Technology Inc.
FIGURE 15-2: EUSART RECEIVE BLOCK DIAGRAM
The operation of the EUSART module is controlled
through three registers:
Transmit Status and Control (TXSTA)
Receive Status and Control (RCSTA)
Baud Rate Control (BAUDCTL)
These registers are detailed in Register 15-1,
Register 15-2 and Register 15-3, respectively.
For all modes of EUSART operation, the TRIS control
bits corresponding to the RX/DT and TX/CK pins should
be set to1’. The EUSART control will automatically
reconfigure the pin from input to output, as needed.
RX/DT pin
Pin Buffer
and Control
SPEN
Data
Recovery
CREN OERR
FERR
RSR Register
MSb
LSb
RX9D
RCREG Register
FIFO
Interrupt
RCIF
RCIE
Data Bus
8
Stop
START
(8) 7 10
RX9
• • •
SPBRGSPBRGH
BRG16
RCIDL
FOSC
÷ n
n
+ 1
Multiplier x4 x16 x64
SYNC 1X00 0
BRGH X110 0
BRG16 X101 0
Baud Rate Generator