Datasheet

PIC18(L)F1XK22
DS41365E-page 142  2009-2011 Microchip Technology Inc.
14.3 I
2
C Mode
The MSSP module in I
2
C mode fully implements all
master and slave functions (including general call
support) and provides interrupts on Start and Stop bits
in hardware to determine a free bus (multi-master
function). The MSSP module implements the standard
mode specifications as well as 7-bit and 10-bit
addressing.
Two pins are used for data transfer:
• Serial clock – SCL
• Serial data – SDA
FIGURE 14-7: MSSP BLOCK DIAGRAM
(I
2
C™ MODE)
14.3.1 REGISTERS
The MSSP module has seven registers for I
2
C
operation. These are:
• MSSP Control Register 1 (SSPCON1)
• MSSP Control Register 2 (SSPCON2)
• MSSP Status register (SSPSTAT)
• Serial Receive/Transmit Buffer Register
(SSPBUF)
• MSSP Shift Register (SSPSR) – Not directly
accessible
• MSSP Address Register (SSPADD)
• MSSP Address Mask (SSPMSK)
SSPCON1, SSPCON2 and SSPSTAT are the control
and STATUS registers in I
2
C mode operation. The
SSPCON1 and SSPCON2 registers are readable and
writable. The lower 6 bits of the SSPSTAT are read-only.
The upper two bits of the SSPSTAT are read/write.
SSPSR is the shift register used for shifting data in or
out. SSPBUF is the buffer register to which data bytes
are written to or read from.
When the MSSP is configured in Master mode, the
SSPADD register acts as the Baud Rate Generator
reload value. When the MSSP is configured for I
2
C
Slave mode the SSPADD register holds the slave
device address. The MSSP can be configured to
respond to a range of addresses by qualifying selected
bits of the address register with the SSPMSK register.
In receive operations, SSPSR and SSPBUF together
create a double-buffered receiver. When SSPSR
receives a complete byte, it is transferred to SSPBUF
and the SSPIF interrupt is set.
During transmission, the SSPBUF is not
double-buffered. A write to SSPBUF will write to both
SSPBUF and SSPSR.
Note: The user must configure these pins as
inputs with the corresponding TRIS bits.
Read Write
SSPSR Reg
Match Detect
SSPADD Reg
Start and
Stop bit Detect
SSPBUF Reg
Internal
Data Bus
Addr Match
Set, Reset
S, P bits
(SSPSTAT Reg)
SCK/SCL
SDI/SDA
Shift
Clock
MSb
LSb
SSPMSK Reg