Datasheet

PIC18(L)F1XK22
DS41365E-page 112  2009-2011 Microchip Technology Inc.
In addition to the expanded range of modes available
through the CCP1CON register and ECCP1AS
register, the ECCP module has two additional registers
associated with Enhanced PWM operation and
auto-shutdown features. They are:
• PWM1CON (Dead-band delay)
• PSTRCON (output steering)
13.1 ECCP Outputs and Configuration
The enhanced CCP module may have up to four PWM
outputs, depending on the selected operating mode.
These outputs, designated P1A through P1D, are
multiplexed with I/O pins on PORTC. The outputs that
are active depend on the CCP operating mode
selected. The pin assignments are summarized in
Table 13-2.
To configure the I/O pins as PWM outputs, the proper
PWM mode must be selected by setting the P1M<1:0>
and CCP1M<3:0> bits. The appropriate TRISC
direction bits for the port pins must also be set as
outputs.
13.1.1 CCP MODULE AND TIMER
RESOURCES
The CCP modules utilize Timers 1, 2 or 3, depending
on the mode selected. Timer1 and Timer3 are available
to modules in Capture or Compare modes, while
Timer2 is available for modules in PWM mode.
TABLE 13-1: CCP MODE – TIMER
RESOURCE
The assignment of a particular timer to a module is
determined by the Timer-to-CCP enable bits in the
T3CON register (Register 12-1). The interactions
between the two modules are summarized in
Figure 13-1. In Asynchronous Counter mode, the
capture operation will not work reliably.
13.2 Capture Mode
In Capture mode, the CCPR1H:CCPR1L register pair
captures the 16-bit value of the TMR1 or TMR3
registers when an event occurs on the corresponding
CCP1 pin. An event is defined as one of the following:
• every falling edge
• every rising edge
• every 4th rising edge
• every 16th rising edge
The event is selected by the mode select bits,
CCP1M<3:0> of the CCP1CON register. When a cap-
ture is made, the interrupt request flag bit, CCP1IF, is
set; it must be cleared by software. If another capture
occurs before the value in register CCPR1 is read, the
old captured value is overwritten by the new captured
value.
13.2.1 CCP PIN CONFIGURATION
In Capture mode, the appropriate CCP1 pin should be
configured as an input by setting the corresponding
TRIS direction bit.
13.2.2 TIMER1/TIMER3 MODE SELECTION
The timers that are to be used with the capture feature
(Timer1 and/or Timer3) must be running in Timer mode or
Synchronized Counter mode. In Asynchronous Counter
mode, the capture operation may not work. The timer to
be used with each CCP module is selected in the T3CON
register (see Section 13.1.1 “CCP Module and Timer
Resources”).
13.2.3 SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep the
CCP1IE interrupt enable bit clear to avoid false inter-
rupts. The interrupt flag bit, CCP1IF, should also be
cleared following any such change in operating mode.
CCP/ECCP Mode Timer Resource
Capture Timer1 or Timer3
Compare Timer1 or Timer3
PWM Timer2
Note: If the CCP1 pin is configured as an output,
a write to the port can cause a capture
condition.