Datasheet

PIC18(L)F1XK22
DS41365E-page 100  2009-2011 Microchip Technology Inc.
10.1 Timer1 Operation
Timer1 can operate in one of the following modes:
•Timer
• Synchronous Counter
• Asynchronous Counter
The operating mode is determined by the clock select
bit, TMR1CS of the T1CON register. When TMR1CS is
cleared (= 0), Timer1 increments on every internal
instruction cycle (F
OSC/4). When the bit is set, Timer1
increments on every rising edge of either the Timer1
external clock input or the Timer1 oscillator, if enabled.
When the Timer1 oscillator is enabled, the digital
circuitry associated with the OSC1 and OSC2 pins is
disabled. This means the values of TRISA<5:4> are
ignored and the pins are read as ‘0’.
FIGURE 10-1: TIMER1 BLOCK DIAGRAM
T1SYNC
TMR1CS
T1CKPS<1:0>
Sleep Input
F
OSC/4
Internal
Clock
On/Off
Prescaler
1, 2, 4, 8
Synchronize
Detect
1
0
2
OSC1/T13CKI
OSC2
1
0
TMR1ON
TMR1L
Set
TMR1IF
on Overflow
TMR1
High Byte
Clear TMR1
(CCP Special Event Trigger)
Timer1 Oscillator
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
On/Off
Timer1
Timer1 Clock Input
T1OSCEN
(1)
INTOSC
Without CLKOUT