Datasheet

PIC18F/LF1XK50
DS41350E-page 88 Preliminary  2010 Microchip Technology Inc.
TABLE 9-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values on
page
PORTA
— —
RA5
(1)
RA4
(1)
RA3
(2)
—
RA1
(3)
RA0
(3)
288
LATA
— —LATA5
(1)
LATA4
(1)
— — — —288
TRISA — — TRISA5
(1)
TRISA4
(1)
— — — —288
ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 — — —288
SLRCON
— — — — — SLRC SLRB SLRA 288
IOCA — —IOCA5IOCA4
IOCA3
(2)
—
IOCA1
(3)
IOCA0
(3)
288
WPUA
— —WPUA5WPUA4
WPUA3
(2)
— — —288
UCON
—
PPBRST SE0 PKTDIS USBEN RESUME SUSPND
—288
INTCON
GIE/GIEH PEIE/GIEL TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF 285
INTCON2 RABPU
INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RABIP 285
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA.
Note 1: RA<5:4> and their associated latch and data direction bits are enabled as I/O pins based on oscillator
configuration; otherwise, they are read as ‘0’.
2: Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0).
3: RA1 and RA0 are only available as port pins when the USB module is disabled (UCON<3> = 0).