Datasheet

 2010 Microchip Technology Inc. Preliminary DS41350E-page 385
PIC18F/LF1XK50
TABLE 27-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,
AND BROWN-OUT RESET PARAMETERS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C T
A +125°C
Param
No.
Sym Characteristic Min Typ† Max Units Conditions
30 TMCLMCLR Pulse Width (low) 2
5
—
—
—
—
s
s
VDD = 3.3-5V, -40°C to +85°C
V
DD = 3.3-5V
31 TWDT Standard Watchdog Timer Time-out
Period
(5)
10
10
17
17
27
30
ms
ms
VDD = 3.3V-5V, -40°C to +85°C
V
DD = 3.3V-5V
31A T
WDTLP Low Power Watchdog Timer
Time-out Period
10
10
18
18
27
33
ms
ms
VDD = 3.3V-5V, -40°C to +85°C
V
DD = 3.3V-5V
32 TOST Oscillator Start-up Timer Period
(1), (2)
— 1024 — Tosc (Note 3)
33* T
PWRT Power-up Timer Period, PWRTE = 0 40 65 140 ms
34* TIOZ I/O high-impedance from MCLR Low
or Watchdog Timer Reset
——2.0s
35 V
BOR Brown-out Reset Voltage 1.8
2.09
2.57
2.71
1.9
2.2
2.7
2.85
2.05
2.35
2.85
3.0
V
V
V
V
BORV = 1.9V
BORV = 2.2V
BORV = 2.7V
BORV = 2.85V
36* V
HYST Brown-out Reset Hysteresis 25 50 75 mV -40°C to +85°C
37* TBORDC Brown-out Reset DC Response
Time
0140sVDD  VBOR
Legend: TBD = To Be Determined
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: Instruction cycle period (T
CY) equals four times the input oscillator time base period. All specified values are
based on characterization data for that particular oscillator type under standard operating conditions with the
device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or
higher than expected current consumption. All devices are tested to operate at “min” values with an external
clock applied to the OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no
clock) for all devices.
2: By design.
3: Period of the slower clock.
4: To ensure these voltage tolerances, V
DD and VSS must be capacitively decoupled as close to the device as
possible. 0.1 F and 0.01 F values in parallel are recommended.
5: Design Target. If unable to meet this target, the maximum can be increased, but the minimum cannot be
changed.